International Business Machines Corporation

John Edward Florkey

Douglas Duane Coolbaugh

Anil Kumar Chinthakindi

Kunal Vaed

Anthony K Stamper

Jeffrey P Gambino

Zhong-Xiang He

Robert Mark Rassel

Richard Paul Volant

Ebenezer E Eshun

Robert Allen Groves

Peter A Smith

Christopher M Schnabel

Keith Edward Downes

Heidi L Greer

The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.

Method of fabricating a precision buried resistor

A semiconductor structure. The semiconductor structure includes: a substrate having at least one metal wiring level within the substrate; an insulative layer on a surface of the substrate; an inductor within the insulative layer; and a wire bond pad within the insulative layer. The inductor and the wire bond pad are substantially co-planar. The inductor has a height greater than a height of the wire bond pad.

Post last wiring level inductor using patterned plate process

A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above a top surface of the substrate; an insulative layer on and above a top surface of the capping layer; an inductor comprising a first portion in and above the insulative layer and a second portion only above the insulative layer; and a wire bond pad within the insulative layer, wherein the first portion the inductor has a height in a first direction greater than a height of the wire bond pad in the first direction, wherein the first direction is perpendicularly directed from the top surface of substrate toward the insulative layer.

Carriers () holding parts () for assembling complex MEMS devices are transported to a central assembly location. The parts are stacked in a pre-assigned order and later released from their carriers. Alternatively, they are positioned over the appropriate location and released so as to fall into position as needed. The assembly area () includes a cavity below the plane of the carriers such that the parts held within the carrier drop into the cavity. Heating elements are integrated into the cavity to assist in the release of the parts. The cavity is supplied with parts by one or more carriers which are move around by any number of MEMS drive systems (). The cavity and some of the MEMS assembled therein deliver with precision amounts of materials as required suitable for biomedical applications, or may be processed in-situ, as in an on-chip laboratory.

Micro-electromechanical sub-assembly having an on-chip transfer mechanism

A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An inductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor.

A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.

Polysilicon containing resistor with enhanced sheet resistance precision and method for fabrication thereof

A semiconductor structure. The semiconductor structure includes: a substrate having a metal wiring level within the substrate; a capping layer on and above the substrate; an insulative layer on and above the capping layer; a first layer of photo-imagable material on and above the insulative layer; a layer of oxide on and above the first layer of photo-imagable material; a second layer of photo-imagable material on and above the layer of oxide; an inductor; and a wire bond pad. A first portion of the inductor is in the second layer of photo-imagable material, the layer of oxide, the first layer of photo-imagable material, the insulative layer, and the capping layer. A second portion of the inductor is in only the second layer of photo-imagable material. The wire bond pad in only the first layer of photo-imagable material, the insulative layer, and the capping layer.

A method of forming a semiconductor structure, and the semiconductor structure so formed, wherein a transmission line, such as an inductor, is formed on a planar level above the surface of a last metal wiring level.

Various methods of fabricating a high precision, silicon-containing resistor in which the resistor is formed as a discrete device integrated in complementary metal oxide semiconductor (CMOS) processing utilizing low temperature silicidation are provided. In some embodiments, the Si-containing layer is implanted with a high dose of ions prior to activation. The activation can be performed by the deposition of a protective dielectric layer, or a separate activation anneal. In another embodiment, a highly doped in-situ Si-containing layer is used thus eliminating the need for implanting into the Si-containing layer.

Low tolerance polysilicon resistor for low temperature silicide processing

A micro-electro mechanical (MEM) switch capable of inductively coupling and decoupling electrical signals is described. The inductive MEM switch consists of a first plurality of coils on a movable platform and a second plurality of coils on a stationary platform or substrate, the coils on the movable platform being above or below those in the stationary substrate. Coupling and decoupling occurs by rotating or by laterally displacing the coils of the movable platform with respect to the coils on the stationary substrate. Diverse arrangements of coils respectively on the movable and stationary substrates allow for a multi-pole and multi-position switching configurations. The MEM switches described eliminate problems of stiction, arcing and welding of the switch contacts. The MEMS switches of the invention can be fabricated using standard CMOS techniques.

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Pleasant Valley, NY, United States of America

John Edward Florkey