International Business Machines Corporation

Other

John Edward Derrick

Lee Evan Eisen

Christopher M Herring

Hung Qui Le

Brian R Konigsburg

David S Levitan

Larry Edward Thatcher

Robert Greg McDonald

William R Greer

Robert William Hay

James Allan Kahle

Paul Joseph Jordan

Kevin Franklin Reick

David James Shippy

Alexander Erik Mericas

Joel Roger Davidson

Henry Chin

George Totolos, Jr

Kevin Lee Sherman

Soummy A Mallick

A method and apparatus for selecting an instruction to be monitored within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate instructions that are eligible for sampling. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. The matched instructions may be marked using a match bit that accompanies the instruction through the selection process. The instructions eligible for sampling are then sampled to generate a sampled instruction. A sampled instruction may be marked with a sample bit that accompanies the instruction through the instruction execution process in order to monitor the sampled instruction while it is executing within the pipelined processor.

Method and apparatus for instruction sampling for performance monitoring and debug

A generalized, programmable dataflow state-machine is provided to receive information about a particular string instruction. The string instruction is parsed into all the operations contained in the string instruction. The operations that make up the string instruction are routed to parallel functional units and executed. The state-machine manipulates the size of the operations in the string instruction and whether or not the instructions need to be generated.

Compressed string and multiple generation engine

An XER scoreboard function is provided by utilizing the instruction sequencer unit scoreboard. A scoreboard bit is set if the XER is being used by a previous instruction. If a new instruction is fetched that uses the XER, a dummy read to the XER is generated to test the scoreboard bit to determine if the scoreboard bit is set. If the scoreboard bit is not set when the dummy read is executed, the X-form string proceeds to execution. If the scoreboard bit is set when the dummy is executed, the pipeline is stalled until the scoreboard bit is cleared, and then the X-form string padded with generated padding IOPs (Dummy or NOPs) is executed. After an accessing instruction is executed, the scoreboard bit is cleared.

Scoreboard mechanism for serialized string operations utilizing the XER

A method and system for optimizing execution of an instruction stream which includes a very long instruction word (VLIW) dispatch group in which ordering is not maintained is disclosed. The method and system comprises examining an access which initiated a flush operation; capturing an indice related to the flush operation; and causing all storage access instructions related to this indice to be dispatched as single-IOP groups until the indice is updated. Storage access to address space which is safe such as Guarded (G&equals;1) or Direct Store (E&equals;DS) must be handled in a non-speculative manner such that operations which could potentially go to volatile I/O devices or control locations that do not get processed out of order. Since the address is not known in the front end of the processor, this can only be determined by the load store unit or functional block which performs translation. Therefore, if a flush occurs for these conditions, in accordance with the present invention the value of the base register (RA) is latched and subsequent loads and stores which use this base register are decoded in a &ldquo;safe&rdquo; manner until an instruction is decoded which would change the base register value (safe means an internal instruction sequence which can be executed in order without repeating any accesses). The value of multiple base registers can be tracked in this manner, though the preferred embodiment would not use more than two, one of the base registers could be for input and one could be for output streams.

Optimization of instruction stream execution that includes a VLIW dispatch group

A transfer tag is generated by the Instruction Fetch Unit and passed to the decode unit in the instruction pipeline with each group of instructions fetched during a branch prediction by a fetcher. Individual instructions within the fetched group for the branch pipeline are assigned a concatenated version (group tag concatenated with instruction lane) of the transfer tag which is used to match on requests to flush any newer instructions. All potential instruction or Internal Operation latches in the decode pipeline must perform a match and if a match is encountered, all valid bits associated with newer instructions or internal operations upstream from the match are cleared. The transfer tag representing the next instruction to be processed in the branch pipeline is passed to the Instruction Dispatch Unit. The Instruction Dispatch Unit queries the branch pipeline to compare its transfer tag with transfer tags of instructions in the branch pipeline. If the transfer tag matches a branch instruction tag the Instruction Decode Unit is stalled until the branch instruction is processed thus, providing a synchronizing method for the parallel pipelines.

Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor

A dummy instruction is issued, followed by several groups of No Operations (NOPs). The instruction sequencer unit (ISU) detects the dummy instruction and stalls the pipeline until the scoreboard indicates the XER count is valid. After a read from a scoreboarded Special Purpose Register (SPR), No Operation&mdash;Internal Operations (NOP&mdash;IOPs) are inserted between write and read SPR IOPs to allow an ISU scoreboard mechanism to be activated before being tested by a read SPR IOP. A read-write-read sequence is utilized: a dummy read of the string count field from a scoreboarded SPR, writing that value back to the same SPR and then performing a read of the SPR once again. A predetermined number of dummy IOPs follow the initial dummy read to prevent the value of the string count field from being read too soon.

Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs

A method and system for aligning internal operations (IOPs) for dispatch are disclosed. The method and system comprise conditionally asserting a predecode based on a particular dispatch slot that an instruction is going to be placed. The method and system further include using the information related to the predecode to expand an instruction into at least one dummy operation and an IOP operation whenever the instruction would not be supported in the particular dispatch slot.

System and method for utilizing a conditional split for aligning internal operation (IOPs) for dispatch

A &ldquo;soft-patch&rdquo; allows an instruction or group of instructions to be replaced with a pre-loaded instruction or group of instructions. When an Instruction Fetch Unit (IFU) fetches an instruction, the instruction is sent through a Compare and Mask (CAM) circuit which masks and compares, in parallel, the instruction with up to eight pre-defined masks and values. The masks and values are pre-loaded by a service processor to CAM circuits which are located in an Instruction Dispatch Unit (IDU) and the IFU in the central processor. An instruction that is deemed a match, is tagged by the IFU as a &ldquo;soft-microcode&rdquo; instruction. When the IDU receives the soft-microcode instruction for decoding, it detects the soft microcode marking and sends the marked instruction to a soft-microcode unit; a separate parallel pipeline in the IDU. The soft-microcode unit then sends the instruction through a CAM circuit which returns an index (or address) for RAM. The index is used to read values out of IDU RAM and generate replacement instructions. Additionally, an Internal Operation that will cause the processor core to perform an unconditional branch to a fixed real address, can be loaded into the IDU RAM allowing an instruction to be replaced by a subroutine or handler routine contained outside the processor core.

Method and apparatus for modifying instruction operations in a processor

A method and system for assigning unique branch tag (BTAG) values in a decode unit in a processing system are disclosed. The method and system comprise providing at least one BTAG value and incrementing the at least one BTAG value for each fetch group as required. The method includes allowing the decode unit to generate the appropriate BTAG values for all dispatch groups formed by instructions within the same fetch group. In the preferred implementation, the BTAG values comprise a major branch tag and two minor branch tags, a count branch tag, and a link branch tag. The &ldquo;seed&rdquo; value for each of the BTAGs is provided each time a branch redirection occurs. Because the branches are passed to the decode unit with little or no processing by the instruction fetch unit, and conditions can cause the branch execution to be delayed, more branches could be decoded and processed than the number of branch entry queues in the instruction fetch unit. Therefore the value of the next entry in the branch entry queue is broadcast to the decode unit and whenever the current branch in the last stage of the decode unit is identical to the broadcast value, the decode unit ceases to process any output instructions until the broadcast value changes.

Simplified method to generate BTAGs in a decode unit of a processing system

A superscalar processor and method are disclosed for efficiently recovering from misaligned data addresses. The processor includes a memory device partitioned into a plurality of addressable memory units. Each of the plurality of addressable memory units has a width of a first plurality of bytes. A determination is made regarding whether a data address included within a memory access instruction is misaligned. The data address is misaligned if it includes a first data segment located in a first addressable memory unit and a second data segment located in a second addressable memory unit where the first and second data segments are separated by an addressable memory unit boundary. In response to a determination that the data address is misaligned, a first internal instruction is executed which accesses the first memory unit and obtains the first data segment. A second internal instruction is executed which accesses the second memory unit and obtains the second data segment. The first and second data segments are merged together. All of the instructions executed by the processor are constrained by the memory boundary and do not access memory across the memory boundary.

Superscaler processor and method for efficiently recovering from misaligned data addresses

A method and system for determining if a dispatch slot is required in a processing system is disclosed. The method and system comprises a plurality of predecode bits to provide routing information and utilizing the predecode bits to allow instructions to be directed to specific decode slots and to obey dispatch constraints without examining the instructions. The purpose of this precode encoding system scheme is to provide the most information possible about the grouping of the instructions without increasing the complexity of the logic which uses this information for decode and group formation. In a preferred embodiment, pre-decode bits for each instruction that may be issued in parallel are analyzed and the multiplexer controls are retained for each of the possible starting positions within the stream of instructions.

Method and system for optimizing the fetching of dispatch groups in a superscalar processor

An apparatus and method for renaming a plurality of storage register files implemented. A rename register in a unified rename buffer provides temporary storage for instruction operands resulting from the execution of the instruction to the operands being written to an architected register in one of storage register files. A rename map associates the rename register with the corresponding storage register, which may be in any of the storage register files. The rename registers may simultaneously store data values of different types. Rename map entries include a tag which operates to identify the register file containing the storage register.

Mechanism for multiple register renaming and method therefor

Buffers are provided in a computer system to allow posting data to the buffers, followed by concurrent operation by different portions of the computer system. A CPU buffer is provided to buffer CPU accesses, a CPU-to-PCI buffer is provided to buffer CPU accesses to the PCI local bus, and a memory buffer is provided to buffer CPU accesses to main memory. This configuration allows the CPU-to-PCI buffer to write data concurrently with the memory buffer accessing data from main memory.

Computer system buffers for providing concurrency and avoid deadlock

Computer system buffers for providing concurrency between CPU accesses,

In a computer system, a multi-port bus controller interposed between a CPU, system memory, and an expansion bus detects when a CPU access is to non-cacheable address space and begins a bus cycle to access the data before receiving a 'miss' from a cache coupled to the CPU. By detecting non-cacheable address space independently and in parallel with the cache miss determination, the multi-port bus controller saves from one to three clock cycles in each bus cycle that accesses non-cacheable address space.

Growing community of inventors

Round Rock, TX, United States of America

John Edward Derrick