International Business Machines Corporation

Synopsys, Inc.

Globalfoundries Inc.

Invecas, Inc.

Infineon Technologies Ag

John Edward Barth, Jr

Dharmendra S Modha

Herbert Lei Ho

Harold Pilo

John Vernon Arthur

Paul A Merolla

Babar Ali Khan

Subramanian Srikanteswara Iyer

Kerry Bernstein

Andrew S Cassidy

Rodrigo Alvarez-Icaza Rivera

Kangguo Cheng

Paul Christian Parries

Darren Lane Anand

Kirk David Peterson

John Atkinson Fifield

Howard L Kalter

William Robert Reohr

Dean L Lewis

Ali Khakifirooz

Brent A Anderson

Reinaldo Ariel Vega

Kern Rim

Michael Richard Ouellette

Jun Sawada

Kevin William Gorman

Bryan L Jackson

Francis Roger White

Edward J Nowak

Geng Wang

Donald W Plass

Matthew R Wordeman

Steven Frederick Oakland

Ethan Harrison Cannon

Jeffrey H Dreibelbis

Vinod Ramadurai

Bruce Bennett Doris

Shom Ponoth

Toshiaki Kirihata

Ravikumar Ramachandran

Wayne Frederick Ellis

William Paul Hovis

Michael Sperling

Kehan Tian

Scott C Lewis

Hoki Kim

Erik A Nelson

Charles E Drake

Daniel J Nickel

James A Yankosky

Adis Vehabovic

Matthew Christopher Lanahan

Jeffrey C Herbert

Peter Kwang Lee

William R Tonti

Ramachandra Divakaruni

Jed Hickory Rankin

Lars W Liebmann

Philip George Emma

Robert C Wong

Vijayalakshmi Srinivasan

Hillery C Hunter

Randy William Mann

Johnathan E Faltermeier

George Maria Braceras

Erik L Hedberg

Peter Anthony Sandon

David E Lackey

Donald Lawrence Wheater

Deok-kee Kim

Shishir Kumar

Andrew A Turner

Douglas Wayne Kemerer

Mark David Jacunski

Norman Whitelaw Robson

Anurag Garg

John B DeForge

Kenneth J Reyer

Pamela Sue Gillis

Abraham Mathews

Srivatsan Chellappa

Arnold S Tran

Gordon A Kelley, Jr

Derek H Leu

Geordie M Braceras

Gerald P Pomichter

Peter O Jakobsen

Yotaro Mori

Jennifer E Appleyard

Rex Ngo Kho

Wayne M Trickle

Michael Lee

Charles H Stapper

Robert Thomas Sayah

Mesut Meterelliyoz

Stephen F Sliva

John Stuart Parenteau, Jr

Kapil Dev Dwivedi

A memory device includes clock signal generation circuitry, and first integrated level shifter and latch circuitry. The clock signal generation circuitry receives a first clock signal and an isolation signal, and generates a second clock signal based on the first clock signal and the isolation signal. The isolation signal corresponds to a power state of a power supply associated with the first clock signal. The first integrated level shifter and latch circuitry receives an input signal in a first power supply domain, and latches a value the input signal based on the second clock signal. Further, the first integrated level shifter and latch circuitry outputs, based on the latched value, an output signal in a second power supply domain different than the first power supply domain.

Interface level-shifter dual-rail memory architecture

A system and method for generating a netlist of a memory device includes receiving a logical netlist file including memory instances and placement information for the memory device. Each memory instance includes leaf cells. Further, a location of a first leaf cell and a location of a second leaf cell of the leaf cells of a first memory instance is determined based on the placement information. A first net segment between the first leaf cell and the second leaf cell is generated based on the location and parasitic elements of the first leaf cell and the location and parasitic elements of the second leaf cell. A parasitic netlist is generated based on the first net segment and the parasitic elements of the first leaf cell and parasitic elements of the second leaf cell.

Transforming a logical netlist into a hierarchical parasitic netlist

A level shifter circuit includes a first current mirror coupled between a power terminal and a ground terminal, a second current mirror coupled between the power terminal and the ground terminal, and a level shifter. The level shifter includes a first transistor coupled to the first current mirror and a second transistor coupled to the second current mirror. The first current mirror and the second current mirror control a state of the first transistor and the second transistor.

Non-fighting level shifters

A system and method for characterizing a memory instance. Characterizing a memory instance includes obtaining a memory instance comprising a plurality of leaf cells. Each of the plurality of leaf cells comprises components. First channel connected components from the components within each of the plurality of leaf cells are determined, and a first super leaf cell is generated by combining a first two or more leaf cells of the plurality of leaf cells based on the first channel connected components. Further, an updated memory instance is generated based on the first super leaf cell, and a timing model is determined for the updated memory instance.

Memory instance reconfiguration using super leaf cells

Embodiments of the invention relate to providing transposable access to a synapse array using a recursive array layout. One embodiment comprises maintaining synaptic weights for multiple synapses connecting multiple axons and multiple neurons, wherein the synaptic weights are maintained based on a recursive array layout. The recursive array layout facilitates transposable access to the synaptic weights. A neuronal spike event between an axon and a neuron is communicated via a corresponding connecting synapse by accessing the synaptic weight of the corresponding connecting synapse in the recursive array layout.

Providing transposable access to a synapse array using a recursive array layout

A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.

Memory bypass function for a memory

An array organization and architecture for a content addressable memory (CAM) system. More specifically, a circuit is provided for that includes a first portion of the CAM configured to perform a first inequality operation implemented between 1 to n CAM entries. The circuit further includes a second portion of the CAM configured to perform a second inequality operation implemented between the 1 to n CAM entries. The first portion and the second portion are triangularly arranged side by side such that the first inequality operation and the second inequality operation are implemented between the 1 to n CAM entries using the same n wordlines.

Array organization and architecture to perform range-match operations with content addressable memory (CAM) circuits

Embodiments of the invention relate to processor arrays, and in particular, a processor array with interconnect circuits for bonding semiconductor dies. One embodiment comprises multiple semiconductor dies and at least one interconnect circuit for exchanging signals between the dies. Each die comprises at least one processor core circuit. Each interconnect circuit corresponds to a die of the processor array. Each interconnect circuit comprises one or more attachment pads for interconnecting a corresponding die with another die, and at least one multiplexor structure configured for exchanging bus signals in a reversed order.

Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor array

An integrated level-shifter and memory clock is disclosed that minimizes delay of voltage level-shifting from an external clock on a first logic supply voltage to an internal clock on a higher array supply voltage that is pulse-width independent of the external clock used to generate the internal clock. The generation of the internal clock on the higher array supply voltages is accomplished in two stages of logic. An array-tracking timing delay circuit mimics access delay to generate a MRST_P to reset the internal clock on the higher array supply voltage.

Method and apparatus for integrated level-shifter and memory clock

Embodiments of the invention relate to faulty recovery mechanisms for a three-dimensional (3-D) network on a processor array. One embodiment comprises a multidimensional switch network for a processor array. The switch network comprises multiple switches for routing packets between multiple core circuits of the processor array. The switches are organized into multiple planes. The switch network further comprises a redundant plane including multiple redundant switches. Multiple data paths interconnect the switches. The redundant plane is used to facilitate full operation of the processor array in the event of one or more component failures.

Faulty core recovery mechanisms for a three-dimensional network on a processor array

Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array

Embodiments of the invention relate to an array of processor core circuits with reversible tiers. One embodiment comprises multiple tiers of core circuits and multiple switches for routing packets between the core circuits. Each tier comprises at least one core circuit. Each switch comprises multiple router channels for routing packets in different directions relative to the switch, and at least one routing circuit configured for reversing a logical direction of at least one router channel.

Array of processor core circuits with reversible tiers

Growing community of inventors

Williston, VT, United States of America

John Edward Barth, Jr