Motorola Corporation

Sun Microsystems, Inc.

Oracle America, Inc.

John E Zolnowsky

Douglas B MacGregor

David S Mothersole

William C Moyer

Michael W Cruess

Lester M Crudele

William M Keshlear

George R Cameron

Blake Alan Jones

Michael E Spak

Thomas G Gunter

Casper H Dik

Charles L Whittington

Scott Rotondo

Joep J Vesseur

Marvin A Mills, Jr

Richard DeWitt Crisp

Jay A Hartvigsen

Kim H Eckert

Gary W Winiger

William P Laviolette

Edward J Rupp, Ii

Bradford R Wetmore

Devang K Shah

William Young

David S Motersole

A method for executing an executable file. The method includes executing instructions in the executable file by a first process, receiving a write request from a second process to write to the executable file, generating an anonymous file from the executable file in response to the write request, executing the anonymous file by the first process, and accessing the executable file by the second process.

Method and system for executing an executable file

A method for securely accessing an executable file object includes a step in which a request from the target process to access the executable file object is received by an operating system component, and the object is examined for validity before access is allowed. For objects that cannot be validated, the process is run with privileges bounded by the privilege cap, if the privilege cap permits execution of the object.

Unvalidated privilege cap

A method for validating program execution. The method involves identifying a program from a second computer system, obtaining, by a first computer system, a first copy of a page for a file of the program from a second computer system, calculating a hash value for the first copy, storing the first copy in a local memory of the first computer system, storing the hash value for the first copy, and executing the program on the first computer system, where the first copy is removed from the local memory during execution of the program. The method further involves obtaining a second copy of the page from the second computer system, calculating a hash for the second copy, determining whether the hash value for the first copy is equal to the hash value for the second copy, and performing an appropriate action in response to the determination.

Method and system for detecting modified pages

A data structure extension system for dynamically adding extensions to existing data structures without interfering with underlying code. The data structure extension system includes logic that allows a programmer to 'privately' extend fields of existing entries in data structures in the operating system's kernel without interfering with the functionality of the overall data structure for other applications. An extension pointer disposed in the data structure associates each entry of the data structures extended with a respective extension table. The extension table allows for the dynamic addition of non-intefering interfering fields to the data structures. Each extension table entry has corresponding data stored in an external storage unit.

System and method of using extensions in a data structure without interfering with applications unaware of the extensions

The present invention provides a process scheduler or dispatcher for a multiprocessor system for real time applications. This embodiment of the present invention proposes a dispatcher model that maintains a dispatch queue for each processor and a separate global dispatch queue for unbound higher priority real time threads. A processor has its own queue and a dispatcher. Each queue has a separate schedule lock associated with it to protect scheduling operations. A processor's dispatcher selects a thread for execution from one of the queues in the system as a candidate thread to execute. When a candidate thread is selected for execution, the processor proceeds to verify against threads in the global real time queue and the processor's own dispatch queue to select a highest priority runnable thread in the system. Thus, the present invention allows the dispatcher to prevent race conditions and minimize lock contention while assuring that high-priority threads are dispatched as quickly as possible. The present invention is implemented by a synchronization between the operations of dispatching a thread and making a thread runnable.

Real time thread dispatcher for multiprocessor applications

A system for properly delivering an signals in a computer system. A first module is called which waits for a signal to be generated. Upon a signal being generated, the first module is notified of the signal's generation. The first module then directs the signal to a second module, and causes the signal to be delivered to the second module.

Generation and delivery of signals in a two-level, multithreaded system

A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

Coprocessor instruction format

Method and apparatus for interrupting a coprocessor

A paged memory management unit (PMMU) adapted to translate each of a plurality of logical addresses into a corresponding physical address using a selected one of a plurality of descriptors comprising one or more translation tables stored in a memory, the PMMU assembling each of the logical addresses and the corresponding physical address into a respective translator. In general, the PMMU includes: a cache having a plurality of storage locations for storing the translators, each of the storage locations including a write protect indicator and a read protect indicator adapted to be selectively set; translation control logic for storing an assembled translator in a selected one of the storage locations, the translation control logic setting the write protect indicator of the one storage location in response to a write protect signal associated with the descriptor used to assemble the translator and the read protect indicator of the one storage location in response to a read protect signal associated with that descriptor; and access control logic for preventing the translator from being used to translate the logical address in support of a write operation if the write protect indicator of the one storage location is set or in support of a read operation if the read protect indicator of the one storage location is set. In the preferred form, the logical address has an access privilege level associated therewith and the descriptor includes a selected write access privilege level and a selected read access privilege level, the translation control logic setting the write protect indicator of the one storage location if the access privilege level associated with the logical address is logically less than the write access privilege level and the read protect indicator of the one storage location if the access privilege level associated with the logical address is logically less than the read access privilege level.

Paged memory management unit which evaluates access permissions when

In a microcoded data processor, an instruction is provided which enables the microaddress for the micromachine to be externally specified. By way of this instruction, the processor may be directed to execute special microcoded routines otherwise unavailable during normal execution. These special microcoded routines may perform useful functions such as testing in an expeditious manner portions of the circuitry of the processor which would otherwise be difficult to test. For example, the functionality of regular structures such as instruction decoding and control programmable logic arrays (PLA's) may either be gated directly out to the tester or internally analyzed before the accumulated results are presented to the tester. On-board instruction caches may also be efficiently exercised to verify that the tag portion properly determines 'hits' and 'misses', and that the actual instruction cache portion functions accurately.

Microcoded processor executing microroutines with a user specified

A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word, Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives whcih define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

Method and apparatus for selectively evaluating an effective address for

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Austin, TX, United States of America

John E Zolnowsky