Honeywell Information Systems Inc.

Bull Hn Information Systems, Inc.

Other

Honeywell Bull, Inc.

John E Wilhite

William A Shelly

Joseph Charles Circello

Charles P Ryan

Ronald E Lange

Donald C Boothroyd

Robert W Norman, Jr

Leonard G Trubisky

Russell Wayne Guenthner

Marion G Porter

Wayne R Buzby

Ronald W Yoder

James L King

Phillip A Angelle

Howard J Keller

Morgan S Riley

A pipelined processor for simultaneously performs one of a plurality of successive operations on each of a plurality of successive instructions within the pipeline, the successive operations including at least an instruction fetch stage, an operand address stage, an operand fetch stage, an execution stage and a result handling stage. The processor also maintains a plurality of indicators which are selectively updated during the result handling stage for a given instruction to reflect the results obtained during the execution stage thereof. When the second instruction of first and second successively fetched instructions is a conditional transfer, a determination is made as to which indicators may be affected by the execution of the first instruction, and a determination is also made as to which indicator the conditional transfer is to test to decide whether there is a GO or a NOGO condition. If the indicator to be tested by the conditional transfer instruction is among those which may be affected by the immediately preceding instruction, the conditional transfer instruction is held at a predetermined stage, for example, in operand addressing, in the pipeline for a predetermined period, such as one full clock cycle, to permit the indicator to be tested to settle before the conditional transfer instruction tests it.

Pipelined central processor incorporating indicator busy sensing and

In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a safestore memory for storing the contents of the plurality of software visible registers, after a data manipulation operation, is provided. Iterative execution instructions subject to a page fault are specially handled in that, during execution, status information indicative of the ongoing status and valid intermediate results are additionally stored in the safestore memory. Then, in the event of a page fault encountered during the execution of the iterative execution instruction, execution is suspended until access to a valid copy of the missing page is obtained. When a valid copy becomes available, the execution of the iterative execution instruction is restarted at the point at which the valid intermediate results had been obtained prior to occurrence of the page fault.

Safestore procedure for efficient recovery following a fault during

In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a shadow set of the software visible registers are used in conjunction with shadowing and packing circuitry for copying the contents of the software visible registers, after a data manipulation operation, into the shadow set after the validity of such contents have been verified. In the event of a detected fault in a data manipulation operation, the contents of the shadow set, which will be the last valid set immediately before the error was detected, are transferred back to the software visible registers to institute recovery at the point in the data manipulation immediately prior to that at which the error was detected. Preferably, packing circuitry is included to pack half-word (or shorter) register information into full words in the shadow set to minimize the number of shadow registers and support circuitry required. In the preferred embodiment, during the recovery process, the safestore information in the shadow set is routed through a cache memory which is normally in direct contact with the working register set such that minimum special circuitry is necessary to restore the contents of the working registers. The speed of recovery is enhanced by the use of double word transfers between the shadow set and the software visible working registers via the cache memory.

Automated safestore stack generation and recovery in a fault tolerant

In order to gather, store temporarily and efficiently deliver (if needed) safestore information in a fault tolerant central processing unit having data manipulation circuitry including a plurality of software visible registers, a shadow set of the software visible registers are used in conjunction with shadowing and packing circuitry for copying the contents of the software visible registers, after a data manipulation operation, into the shadow set after the validity of such contents have been verified. In the event of a detected fault in a data manipulation operation, the contents of the shadow set, which will be the last valid set immediately before the error was detected, are transferred back to the software visible registers to institute recovery at the point in the data manipulation immediately prior to that at which the error was detected. Preferably, packing circuitry is included to pack half-word (or shorter) register information into full words in the shadow set to minimize the number of shadow registers and support circuitry required. In the preferred embodiment, during the recovery process, the safestore information in the shadow set is routed through a cache memory which is normally in direct contact with the working register set such that minimum special circuitry is necessary to restore the contents of the working registers.

Automated safestore stack generation and move in a fault tolerant

A distrbutor for the central execution pipeline unit of a central processor of a data processing system, which central processor has a plurality of execution units. The distributor serves as a communications center by which machine words, such as operands, are transmitted primarily from the cache unit of the central processor unit to execution units and the instruction fetch unit of the central processor unit. Some machine words are transmitted directly from the collector unit to selected units and others are transmitted after being stored in the data register of the distributor. Machine words stored in the data register can be realigned if required by an instruction by character or word alignment switches. The aligned words are then stored in the data register means prior to their being transmitted to units of the central processor. Other sources of signals transmitted by the distributor are the collector unit and registers of the distributor containing the effective address of a target word as calculated by the central execution pipeline unit, as well as copies of machine words in key registers, the A/Q registers, of certain of the execution units.

Distributor of machine words between units of a central processor

The present invention relates to the operational control of a digital computer system which includes the digital logic circuitry for temporarily storing results internal to an execution unit. An input unit of the execution, which inputs operand words to the execution logic of the execution unit, includes a first stack for holding operand words received from an external memory unit and a second stack for holding the result words of the execution logic. The input unit also includes a switch element for selecting words stored in the first and second stack which are to be utilized as input operand words to the execution logic in response to at least one control signal.

Wraparound buffer for repetitive decimal numeric operations

The present invention relates to a method within a digital computer system for reading operand data stored in a temporary storage memory in a forward or reverse direction. The method includes loading the temporary storage memory with the first and second operand data strings in a pre-established order such that the subsequent fetching of the operand data words from the temporary storage memory is performed in a sequential order. The loading and fetching steps operate to achieve a desired word order such that the operation between operand data strings can be started while the operand data is being fetched.

Method for decreasing execution time of numeric instructions

An associative memory used to translate a virtual page number (VPN) of a virtual word address to a physical page number (PPN) of a physical word address of a random access memory of a digital computer system is provided with a pair of independently addressable validity bit arrays, each of which arrays can store a validity bit in each of the addressable locations of each array. A pointer enables only one of the validity bit arrays to receive address signals corresponding to the lower virtual page number (LVPN) of a VPN. The validity bit read out of the memory location corresponding to the LVPN of the enabled array is used in determining if the PPN read out of the corresponding memory location of the associative memory is valid. The bits of the disabled array, immediately after it is disabled, are all reset, or cleared. After all validity bits of the disabled array are reset, a clear associative memory paging (CAMP) instruction can be executed to invalidate all entries written into the associative memory by enabling the cleared disabled array and disabling the array enabled at the time such a CAMP instruction begins execution.

Dual validity bit arrays

Apparatus and method for a supervisor for data processing system capable of utilizing a plurality of operating systems. The supervisor includes apparatus for identifying a condition in the data processing system requiring a different operating system. A reserved memory area associated with the currently active operating system is then addressed and register contents of a central processing unit are stored in the reserved memory area. The reserved memory of the operating system being activated is addressed and causes the address of the reserved memory of the operating system being activated, the data related to permitting the physical memory associated with the operating system being activated, contents of registers safestored in the reserve-memory and, data establishing the decor of the operating system being activated are entered in the central processing unit. The operating system to be activated is then enabled, and execution of permitted instructions by the second operating system is begun. The physical memory locations are determined by a real address through use of a paging mechanism permitting storage of portions of the operating systems in non-contiguous groups of locations while isolating the memory available to each operating system.

Apparatus and method for a data processing unit sharing a plurality of

Apparatus and method for providing an improved instruction buffer associated with a cache memory unit. The instruction buffer is utilized to transmit to the control unit of the central processing unit a requested sequence of data groups. In the current invention, the instruction buffer can store two sequences of data groups. The instruction buffer can store the data group sequence for the procedure currently in execution by the data processing unit and can simultaneously store data groups to which transfer, either conditional or unconditional, has been identified in the sequence currently being executed. In addition, the instruction buffer provides signals for use by the central processing unit defining the status of the instruction buffer.

Instruction buffer associated with a cache memory unit

A method and a central execution pipeline unit for initiating the execution of instructions of a synchronous central processor unit (CPU) of a general-purpose digital data processing system. Instructions containing address information and an instruction field are obtained in program order from an instruction fetch unit of the CPU. In a first stage, requiring one clock period, the address information of an instruction is utilized to form the carrys and sums of an effective address and to initiate the formation of a virtual address. Concurrently, the instruction field is decoded to produce memory command signals and data alignment signals. In a second stage, the formation of the effective and virtual addresses initiated in the first stage is completed, and the word address portion of the virtual address is transmitted to the cache unit of the CPU. Also during the second stage, memory command signals are sent to the cache unit and the instruction field is converted to an execution code for one of a plurality of execution units, and the execution unit to execute the code is designated. In a third stage, the virtual address is converted to a physical address, or real page number, which is transmitted to the cache unit. The execution code is sent to the designated execution unit; however, if the execution unit is the central unit, the execution unit is the central unit, the execution code for that unit is converted into execution unit control signals. In the fourth stage, data alignment control signals are sent to a distributor of the central execution pipeline unit.

Method and apparatus for initiating the execution of instructions using

A data processing system includes a cache store to provide an interface with a main storage unit for a central processing unit. The central processing unit includes a microprogram control unit in addition to control circuits for establishing the sequencing of the processing unit during the execution of program instructions. Both the microprogram control unit and control circuits include means for generating pre-read commands to the cache store in conjunction with normal processing operations during the processing of certain types of instructions. In response to pre-read commands, the cache store, during predetermined points of the processing of each such instruction, fetches information which is required by such instruction at a later point in the processing thereof.

Data processing system programmable pre-read capability

A cache oriented pipeline data processing unit includes an execution unit, apparatus for fetching data and instructions, hardware decoder and sequencing circuits and a microprogrammed control unit. The microprogrammed control unit includes first and second control stores. The first control store includes a plurality of storage locations, each location for storing at least an address field and a control sequence field for each of the program instructions required to be executed by the data processing unit. The control sequence field is coded to designate which one of a group of hardware control sequences is to be executed by the hardware sequencing circuits for matching the performance of the execution unit and fetching apparatus. The second control store includes a plurality of groups of storage locations, each group for storing the microinstructions required for executing at least a portion of a program instruction. The microprogrammed control unit in response to each instruction op-code reads out signals corresponding to a control sequence field which are decoded to condition the hardware sequencing circuits for performing those operations required for execution of the instruction. The starting location in the second control store is referenced at the end of the designated hardware sequence and instruction execution proceeds under microprogram control.

Microprogrammed computer control unit capable of efficiently executing a

A microprogrammed pipeline data processing unit includes a first control store, a second control store and a plurality of hardware sequence control circuits. The first control store includes a plurality of storage locations, each location for storing an address field and a control sequence field for each program instruction required to be executed by the processing unit. The second control store includes a plurality of groups of storage locations, each group storing microinstructions required for executing at least a portion of at least one program instruction. Each sequence includes at least one microinstruction which contains a restart field coded to specify the conditions under which the hardware sequence circuits continue instruction execution. For each program instruction which can not be executed by the plurality of hardware sequence circuits in a pipeline mode, the control sequence field is coded to include a predetermined bit pattern. When decoded, the hardware sequence circuits is conditioned to enter an escape state enabling control to be transferred to a sequence specified by the address field. Instruction execution proceeds under microprogram control while the hardware sequence circuits remain in the same state. Upon the decoding of a microinstruction containing a restart field, the hardware sequence circuits are switched from the escape state to a state which enables the continuing of hardware instruction execution in a pipeline mode.

Hardware controlled transfers to microprogram control apparatus and

A microprogrammable control unit of a data processing unit includes first and second control stores. The first control store which is addressed initially by the operation code of a program instruction is used for storing a predetermined constant field coded to further specify the operation specified by the instruction operation code in addition to a control sequence field and address field. The second store stores a plurality of microinstructions sequences for executing the repertoire of program instructions. Control unit hardware decoder and sequencing circuits are conditioned by the control sequence field to execute a portion of the program instruction at the completion of which control is transferred to the second control store for completing execution of the program instruction under microprogram control. During the processing of various program instructions, the hardware sequencing circuits are operative to load signals corresponding to the constant field selected into one of a plurality of registers of the control unit. The constant signals selectively condition apparatus within the data processing unit enabling the hardware sequencing circuits and sequences of microinstructions from the second control store to execute the operation more particularly specified by the constant field in accordance with the operation code without requiring further decoding of such operation code.

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Glendale, AZ, United States of America

John E Wilhite