General Magic, Inc.

John E Watkins

Stephen G Perlman

Walter F Broedner

Anthony M Faddell

Anthony M Fadell

A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. All bus transactions over the bus occur under bus dispatch commands. If a peripheral device interrupts the bus dispatch, bus dispatch issues commands over the bus to determine which device caused the interrupt and what service is being requested by the device. The bus dispatch may then turn control of the data and clock lines over to the peripheral device for a limited amount of time depending on the service requested. New peripheral devices can be connected onto the bus and unused peripheral devices can be disconnected from the bus while the bus is operating without causing a bus failure. Similarly, bus dispatch may enter a low power sleep mode from which it may be awakened by a peripheral device. In some embodiments, additional lines such as battery charging lines and/or signal lines for other serial buses such as RS-232 and RS-422 are provided.

Method for transmitting bus commands and data over two wires of a serial

A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch in a base station (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. Data and commands are sent from the base station to a peripheral device, and data is received from the peripheral device by the base station by configuring each peripheral device on the bus to receive data and clock signals from the base station in an idle mode of operation. Upon a command send being transmitted by the base station, all peripheral devices on the serial bus between the base station and an addressed peripheral device remain in the idle mode and the addressed peripheral device is connected to the bus so that clock and data signals on the bus to are passed to the peripheral device. When the peripheral devices on the bus are in the idle mode of operation, and the base station transmits a command get to an addressed peripheral device, the addressed peripheral device and all peripheral devices between the addressed peripheral device and the base station are reconfigured to transmit clock and data signals from the addressed peripheral device to the base station.

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San Francisco, CA, United States of America

John E Watkins