Skyworks Solutions, Inc.

Intel Corporation

Marvellworld Trade Ltd.

Mediatek Corporation

John E Vasa

Jaleh Komaili

Thomas Obkircher

Masoud Kahrizi

Morten Damgaard

Norman J Beamish

Darioush Agahi

Balasubramanian Ramachandran

Rajasekhar Pullela

Aly Mamdouh Ismail

Rony Ashkenazi

Alexander Zaslavsky

Tudor Lipan

Shahrzad Tadjpour

Bala Ramachandran

Hoon Lee

Nader Damavandi

Yongqiang He

Masoud Kahirzi

A system provides closed-loop gain control in a WCDMA mode and open loop control in an EDGE/GSM mode. Gain control is distributed across analog devices and a digital scaler in a wireless receiver. In the WCDMA mode, a loop filter generates an error signal that is forwarded to analog and digital control paths. The analog control path includes a first adder, a programmable hysteresis element, and a lookup table. The analog control signal is responsive to thresholds, which when used in conjunction with a previous gain value determine a new gain value. The digital control path includes a second adder, a programmable delay element, and a converter. A control word is responsive to a difference of the error signal, a calibration value, and the analog control signal. Blocker detection is provided in the WCDMA mode of operation. A controller sets system parameters using a state machine.

Circuits, systems, and methods for managing automatic gain control in quadrature signal paths of a receiver

A circuit includes a transmit path to receive an input signal and generate an output signal to be output at a transmit power level according to a power target signal. The circuit also includes a gain corrector to output a signal for adjusting a power level of the output signal to correspond to the transmit power level. The signal for adjusting is based on the power target signal and a delay for time-aligning a first signal and a second signal.

Method for fast automatic power control of wireless transmitters

A transmit signal second-order inter-modulation (IM2) canceller for a portable handset using a full duplex mode of operation (e.g., WCDMA) is used to controllably reduce IM2 introduced by a transmit signal that appears in a received signal in a receive channel of the portable handset. The transmit signal IM2 canceller includes a delay estimator and a digital signal adjuster. The delay estimator receives a first input from a receive channel and a second input from a transmit channel. The delay estimator generates an estimate of the IM2 that the transmit channel introduces in the receive channel. The digital signal adjuster removes the estimate of the IM2 before forwarding a modified receive channel signal to a baseband subsystem of the portable handset.

LMS adaptive filter for digital cancellation of second order inter-modulation due to transmitter leakage

A mobile handset is arranged with an adaptive power controller to controllably adjust transmit power. The adaptive power controller is coupled to a power amplifier module to form a closed feedback loop. The adaptive power control module includes a first shifter, a first sealer, an accumulator and a hold element. The first shifter and first sealer receive respective bandwidth control signals and an error signal. The first shifter and first sealer generate a modified error signal that is forwarded to and filtered by the accumulator and the hold element to generate a power control signal. The power control signal, which is generated the radio frequency subsystem of the handset can quickly and accurately track rapid changes in transmit power.

Closed-loop adaptive power control for adjusting bandwidth in a mobile handset transmitter

A digital modulator for a portable handset using 8PSK or EDGE modulation with a direct launch transmitter is used to controllably adjust the transmit power of the portable handset. The digital modulator includes a controller coupled between a memory and an accumulator. The controller is responsive to an indication that the transmit power should be transitioned. The controller temporarily alters the data transferred from the memory to the accumulator during transitions of the transmit power level.

Digital modulator and method for initiating ramp power transitions in a mobile handset transmitter

A phase-locked loop (PLL) is arranged to receive high-pass data at a first input and low-pass data at a second input. A first digital input is coupled to a primary path through a digital-to-analog converter (DAC) and a second digital input is coupled to a feedback path of the PLL. The controller provides the first input and the second input during a calibration procedure. The controller adjusts first and second control inputs in an attempt to keep the input voltage to a voltage-controlled oscillator (VCO) in the PLL constant while determining the gain of the VCO in Hz/LSB.

Voltage-controlled oscillator gain calibration for two-point modulation in a phase-locked loop

A receiver for a multi-mode wireless device is provided. The receiver has multiple analog RF front end modules, with each module supporting a different mode of operation. The receiver has a single digital backend module for generating a digital baseband signal. A controller selects one of the available RF modules to use, and the selected RF module provides an analog communication signal to the digital backend. Each available mode has an associated set of factors. When a particular mode is selected, the set of factors associated with the selected mode is provided to the digital backend. The digital backend uses these factors to adjust the processing characteristics of its components, such as its analog to digital converter, filters, and gain controller. In this way, the single digital backend is adaptable to the requirements of each of the available radio modes.

Receiver for a multimode radio

A low noise filter is arranged to receive an input signal from a downconverter. The low noise filter is constructed to block or cancel any DC offset in the input signal, as well as filter selected frequency components from the input signal. The low noise filter uses a shared capacitor both to handle the DC offset and to set filter response characteristics. As the low noise filter is implemented with a Frequency Dependent Negative Resistance (FDNR) device, the shared capacitor may be relatively small. The low noise filter has a load capacitor, with the output of the load capacitor coupled to a bias resistor and voltage. This bias structure cooperates with the load capacitor to set a high cutoff frequency for the low noise filter useful for blocking or canceling the DC offset.

Low noise filter for a wireless receiver

A system and method for direct current offset correction are disclosed. One embodiment of the system includes a direct current offset correction circuitry having an adjustable bandwidth and control logic configured to effect a bandwidth change of the direct current offset correction circuitry to speed up warm-up and settling time of the direct current offset correction circuitry.

Direct current offset correction systems and methods

A system for reducing digital-to-analog converter (DAC) resolution for an amplitude modulated signal comprises a first logic configured to determine a desired DAC output voltage range, a second logic configured to select a DAC reference voltage level corresponding to the desired DAC output voltage range, a third logic configured to select a number of digital bits for conversion to the analog domain, the number of bits chosen from a larger number of digital bits, and a DAC configured to receive the selected DAC reference voltage level and convert the selected number of digital bits to a signal in the analog domain.

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Irvine, CA, United States of America

John E Vasa