Lattice Semiconductor Corporation

John E Turner

David Lee Rutledge

Roy D Darling

Gregg R Josephson

Jerome E Liebler

An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retains a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin receives serial input data which loads a shift register latch. The contents of the latch are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed. The device normal inputs and outputs are isolated from the device during the utility states, so that the user's system does not affect the device operation during the utility states. A voltage multiplier circuit is included to generate the high voltage level necessary to program the floating gate transistors employed as the device memory cells from the device supply voltage, thereby further conserving on the required number of device pins. By programming a particular memory cell, the user may select the state of the device outputs during the utility states as either a present data latched condition or a tri-stated condition.

Programmable logic device configurable input/output cell

A data security fuse system is disclosed for allowing one-time programmability of protected data cells in a reprogrammable logic device, which may determine, for example, the logic architecture of the device. The system includes a fuse enable circuit which may be erased to the disabled state only prior to packaging of the device during manufacture. The protected data cells may be selected for programming by a decoder which decodes cell selection signals. A security fuse circuit is enabled by a fuse enable signal from the activated fuse enable circuit. The security fuse circuit allows the protected cells to be selected once for programming after the system has been activated, and thereafter defeats any attempts to access the protected data cells.

One-time programmable data security system for programmable logic device

In-system programmable logic device

An in-system programmable logic device is disclosed which may be configured or reconfigured while installed in a user's system. The disclosed device employs non-volatile memory cells such as floating gate transistors as the programmable elements, and hence the device retain a particular programmed logic configuration virtually indefinitely during a powered-down state. The device is operable in a normal state and in several utility states for reconfiguring the device. The device state is controlled by an internal state machine which executes several state equations whose variables are the logic levels driving two dedicated pins and the present device state. One device pin receives serial input data which loads a shift register latch. The contents of the latch are employed to select a particular row of the cells to be programmed and the logic level to which the selected cells are to be programmed. The device normal inputs and outputs are isolated from the device during the utility states, so that the user's system does not affect the device operation during the utility states. A voltage multiplier circuit is included to generate the high voltage level necessary to program the floating gate transistors employed as the device memory cells from the device supply voltage, thereby further conserving on the required number of device pins. By programming a particular memory cell, the user may select the state of the device outputs during the utility states as either a present data latched condition or a tri-stated condition.

In-system programmable logic device with four dedicated terminals

An architecture security fuse circuit is disclosed for securing the architecture of a configurable programmable logic device. The storage element of the circuit is a floating gate transistor cell. Data stored in the cell is determined by the amount of charge trapped within the oxide-isolated polysilicon floating gate region. The security fuse is initialized (erased) during device fabrication to allow access to device architectural data. Such initialization is accomplished by a technique that the device user cannot duplicate, via an extra probe pad accessible only during wafer probe. To deter the effects of floating gate charge loss which may occur during subsequent fabrication steps, the fuse circuit is adapted to provide a reduced memory cell read voltage, thus providing greater margin against thermally defeating the security fuse. A regenerative feature is provided to strengthen the erased cell during every device 'clear' cycle. Once the security fuse is programmed, the data defining the device architecture may not be interrogated or altered, and the memory cell is unchanged by the regenerative feature.

Programmable data security circuit for programmable logic device

A programmable logic device is disclosed which is adapted to isolate the Miller capacitances of erased memory cells from the product terms and to limit the cell current drawn through the product term sense amplifiers. The invention substantially reduces the row switching noise coupled onto the product terms, allows high speed sense amplifier operation, and significantly reduces the power dissipated by the device. In accordance with the invention, the electrically erasable sense transistor for each memory cell is disposed between the cell select transistor and the product term sense amplifier, thereby isolating the Miller capacitance associated with the select transistor from the sense amplifier when the cell is in the erased (nonconductive) state. Separate product term ground lines are provided for each product term. A current limiter connects each product term ground line to ground, and is adapted to limit the current flow through each product term to a predetermined maximum level, typically about the maximum current level which may be passed through one conductive memory cell.

Programmable logic device with limited sense currents and noise reduction

A programmable logic array is disclosed employing arrays of electrically erasable and programmable cells. The device includes a dual purpose programming circuit which is employed to provide programming data to the AND array to program the AND array cells, and to provide OR array row selection data during OR array programming, thereby eliminating the need for a separate OR array row decoder. A method and apparatus is also disclosed for efficiently testing the AND array cells and input circuitry by bulk stripe programming the array cells.

Programmable logic array

An improved programmable logic device (PLD) is disclosed which employs electrically erasable memory cells which can be programmed and erased at high speed. The PLD memory cells comprise floating gate transistors as the storage elements, which are programmed and erased by Fowler-Nordheim tunneling. The PLD includes a serial register latch (SRL) which is coupled to the product terms of the PLD array. Input programming data for a selected row of the array is serially entered into the SRL, and during a programming cycle the SRL data is employed to simultaneously program the storage elements of the selected row to either the enhancement mode or the depletion mode. The data programmed into the array may be verified at high speed. The status of each of the cells in the selected row can be sensed using the normal sense amplifiers and loaded into the SRL in parallel, and thereafter serially shifted out of the PLD for external verification. The PLD output logic and sense amplifiers can be functionally validated independent of the data in the array. Test data such as apparent array patterns are serially loaded into the SRL, and thereafter forced onto the normal sense amplifier inputs, propagated through the output logic and read out of the device output pin.

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Beaverton, OR, United States of America

John E Turner