Hyundai Electronics America, Inc.

Burroughs, Inc.

Other

John E Spracklen

Bruce D Lightner

Merle A Schultz

Valeri Popescu

Gary A Gibson

Mark L Gerhold

Roy F Quick

Marshall M Parker

Michael A Malcolm

Gary W Hodgman

Lawrence D Rogers

A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.

Processor architecture providing for speculative execution of

Processor architecture providing speculative, out of order execution of

Processor architecture supporting speculative, out of order execution of

Processor architecture providing out-of-order execution

Processor architecture having out-of-order execution, speculative

Processor architecture supporting multiple speculative branches and trap

Processor architecture supporting multiple speculative branching

Processor architecture having independently fetching issuing and

An interconnection circuitry for two local area contention networks which is adapted to jam the respective networks when stations on both sides of the interconnection circuitry attempt transmission. If stations on opposite sides of the interconnect circuitry begin transmitting at the same time, the interconnect circuitry operates to place a high signal on the channel of each network and all stations will detect that the data is garbled and discard it.

Interconnection for local area contention networks

This disclosure relates to a line driver circuit for a station in a data transmission network, which driver circuit is adapted to drive the channel medium with a constant current so that conflicts or collisions with data transmissions from other stations will be cancelled out thereby preventing any particular station from dominating reception of a neighboring station. Each station is adapted to operate in a cyclic mode for contending for access to the network channel where a three-state cycle is employed, which states are the idle state, the packet-being-transmitted state and the acknowledgment period state. Each station will not begin transmission until it determines that the tunnel is in an idle state. Once the station has determined that the channel is idle, it will then delay for a period of time that is randomly chosen and, if the channel is still idle, will then begin transmission. Following transmission, the channel will again be quiescent for a short period of time before the acknowledgment signal is transmitted from the receiver. Each packet of data to be transmitted is of a fixed length so as to provide for synchronization between the various stations contending for access to the channel.

Line driver circuit for a local area contention network

This disclosure relates to a station for a data transmission network which is adapted to operate in a cyclic mode for contending for access to the network channel along with other stations of the network. The three states of the cycle are the idle state, the packet-being-transmitted state and the acknowlegement period state. Each station will not begin transmission until it determines that the channel is in an idle state. Once the station has determined that the channel is idle, it will then delay for a period of time that is randomly chosen and, if the channel is still idle, will then begin transmission. In this way, contention conflicts between stations is minimized without unduly restricting communication between stations. Following transmission, the channel will again be quiescent a short period of time before the acknowledgement signal is transmitted from the receiver. Each packet of data to be transmitted is of a fixed length so as to provide for synchronization between various stations contending for access to the channel.

Local area contention network data communication system

Growing community of inventors

San Diego, CA, United States of America

John E Spracklen