Motorola Corporation

Freescale Semiconductor,inc.

John E Schmiesing

Juergen A Foerstner

Guang X Li

Muh-Ling Ger

Frank A Shemansky, Jr

Paul L Bergstrom

Bich-Yen Nguyen

Bishnu Prasanna Gogoi

Andrew C McNeil

Daniel N Koury, Jr

David Joseph Monk

Henry G Hughes

Bor-Yuan C Hwang

Ronald J Gutteridge

Ljubisa Ristic

John R Alvis

Richard J August

Howard K Leung

Donald L Hughes, Jr

Kevin D Neumann

David W Odle

Andrew C Mcneil

A capacitive pressure sensor ( ) utilizes a diaphragm ( ) that is formed along with forming gates ( ) of active devices on the same semiconductor substrate ( ).

Method of forming an integrated CMOS capacitive pressure sensor

A sensor has an electrode (,) that is movable along three mutually perpendicular axes (,). The sensor also has stationary over-travel limiting structures that restrict the movement of the electrode (,) along the three axes (,).

Sensor and method of use

A sensor has an electrode (120) that is movable along three mutually perpendicular axes (10, 11, 12). The sensor also has stationary over-travel limiting structures that restrict the movement of the electrode (120) along the three axes (10, 11, 12).

An enclosure (8) for an electronic device (26) such as, for example, an accelerometer. The enclosure (8) includes a conductive semiconductor substrate (12) underlying the electronic device (26), a conductive cap (16) overlying the electronic device (26), and a power supply (25) having one or more outputs (27, 29) each with a substantially fixed potential wherein one output is electrically coupled to the conductive semiconductor substrate (12) and another output to the conductive cap (16). In a preferred embodiment, substrate ( 12 ) and cap (16) are coupled to the same power supply output (27). This coupling substantially eliminates the adverse effects of parasitic capacitances of the substrate (12) and cap (16) to reduce measurement error and EMI when a capacitive accelerometer is used as the electronic device (26).

Electronic device enclosure including a conductive cap and substrate

A method for fabricating BiCMOS on SOI. An SOI wafer (14) with an oxide layer (17) and a nitride layer (16) has areas isolated by a LOCOS or mesa isolation (13). A region (15) is defined for CMOS structures from which the insulating layers (17,16) are removed. A gate oxide (21), a polycrystalline silicon layer (22), and a second insulating layer (23,24) is formed. A region for emitters (26) is defined and nitride deposited to form a spacer (27). An oxide layer (28) is grown over the polycrystalline silicon (22) within the emitter region (26). The wafer (14) is etched to the underlying monocrystalline silicon (18) forming base contacts (31). A polycrystalline silicon spacer (36) is formed from a second polycrystalline layer (43) and an oxide spacer (40) is deposited. A region for bipolar collectors (32) and CMOS areas (34) is defined and a spacer (38) deposited.

Complementary bipolar and CMOS on SOI

A process is disclosed for fabricating a semiconductor device which includes a trench formed at the surface of the device substrate. The surface of the device substrate is oxidized and the oxide is patterned to form an opening which exposes a portion of the underlying surface. Ions are implanted through the opening and into the surface to form a damaged surface region which is coincident with the opening and extends under the edge of the oxide. A trench is etched by reactive ion etching using the opening in the oxide as an etch mask. The substrate, including the walls of the trench and the ion implant damaged surface portion under the edge of the oxide, is thermally oxidized. The oxidation rate is enhanced by the damage and causes a thicker oxide to grow in the damaged region which forms a collar around the intersection of the trench with the surface. Upon removing the oxide, the intersection of the trench with the surface is characterized by a rounded corner caused by the enhanced oxidation in that location during the oxidation.

Trench formation process

Growing community of inventors

Tempe, AZ, United States of America

John E Schmiesing