Micron Technology Incorporated

John E Riley

Scott Eugene Smith

Yu-Feng Chen

Joo-Sang Lee

Gary L Howe

Alan John Wilson

Christian N Mohr

Girish N Cherussery

Raghukiran Sreeramaneni

Jennifer E Taylor

Matthew Young

The present disclosure includes apparatus, methods, and systems for error detection for a semiconductor device. An apparatus includes a memory array, a detector array, and a detector coupled to the detector array. The detector is configured to detect an error in a portion of the detector array and output an output signal to memory components coupled to the detector array in response to detecting the error.

Error detection for a semiconductor device

Methods, systems, and devices for adjusting a refresh rate during a self-refresh state are described. A memory system may enter a self-refresh state and execute a first set of refresh operations on a set of rows of memory cells at the memory system according to a first rate. The memory system may determine, based on executing the first set of refresh operations, that a counter associated with the set of refresh operations satisfies a threshold for a second time while the memory system is in the self-refresh state. In response to the counter satisfying the threshold for the second time, a flip-flop circuit at the memory system may modify an output of the flip-flop circuit and the memory system may decrease the rate for executing the refresh operations to a second rate based on the modified output of the flip-flop circuit.

Adjusting refresh rate during self-refresh state

A memory device includes at least one memory bank comprising a set of redundant word lines, a set of normal word lines, and row hammer refresh logic. The RHR logic comprises a first input to receive a first signal indicative of whether a match was generated at a fuse of the memory device, a second input to receive a redundant row address corresponding to a first location of a memory array of the memory device, a third input to receive a word line address corresponding to a second location of the memory array of the memory device. The RHR logic also comprises an output to transmit at least one first memory address adjacent to the first location or at least one second memory address adjacent to the second location based on a value of the first signal.

Systems and methods for capture and replacement of hammered word line address

A portable clothes hanging assembly includes a plurality of brackets attached together to define a wall mount that is attachable to a wall of a room in a building and a hanger extending away from the wall mount. A hanging wheel is rotatably attached to the hanger such that the hanging wheel has a vertical rotational axis. A plurality of hanger supports is provided and each of the hanger supports is suspendable from the hanging wheel. Each of the hanger supports has a plurality of receivers thereby facilitating each of the receivers to receive a respective one of a plurality of clothes hangers. In this way the hanging wheel facilitates the clothes hangers to hang clothes in the absence of a closet.

Portable clothes hanging assembly

Memory devices may have internal circuitry that employs voltages higher and/or lower than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate the higher voltages internally. The number of available charge pumps in a memory device may be conservatively dimensioned to be high, in some systems to protect yields. Some of the available charge pumps may be disabled during manufacturing or testing to reduce the number of active charge pumps. The testing process may employ dedicated logic in the memory device and the disabling may employ fuse circuitry.

Charge pump supply optimization and noise reduction method for logic systems

Methods, apparatuses, and systems related to operations for managing the quality of an input signal received by a device and for providing feedback in real-time. A controller can provide a reference signal to the device for the input quality check. The memory can implement the input quality check by counting the number of transitions of the reference signal for a set time period and store the resulting count value(s). The memory can use the count value(s) to determine a condition or a quality for the reference signal.

Apparatus with input signal quality feedback

Systems and methods to perform multiple row repair mode for soft post-packaging repair of previously repaired data groups are disclosed. The devices may have activation circuitry that includes a mode register bit or a control antifuse that sends an input signal upon activation. The devices may also include a logic element that receives the input signal and sends, upon receiving the input signal, a configuration signal that enables a multiple row repair mode.

Configurable soft post-package repair (SPPR) schemes

A memory device includes a plurality of memory cells and first circuitry coupled the plurality of memory cells, wherein the first circuitry is configured to perform a memory operation on at least one memory cell of the plurality of memory cells. The memory device also includes a charge pump coupled to the first circuitry, wherein the charge pump comprises a pump oscillator configured to generate an oscillator signal having only pulses with a width above a predetermined threshold pulse width and a pump core configured to receive the oscillator signal and a first electrical power signal at a first voltage, generate a second electrical power signal at a second voltage based upon the oscillator signal and the first voltage.

Charge pump supply oscillator

An electronic device including: a fuse array including: fuse elements organized along a first direction and a second direction, wherein each fuse element is configured to store information, and a selection circuit configured to provide access to the fuse elements according to positions of the fuse elements along the first direction and the second direction; and a fuse read circuit connected to the fuse array, the fuse read circuit configured to generate a fuse-read output based on reading from one or more of the fuse elements.

Electronic device with a fuse array mechanism

Systems and methods to perform post-packaging repair of previously repaired data groups are disclosed. The devices may have an array of addressable rows or columns of memory cells, which can be activated. Upon identification of defect in a memory cell row or column, a repair in which the memory cell may be deactivated and a secondary row may be activated in its place may be performed. Volatile and non-volatile storage elements may be used to store the defective memory addresses. Logic circuitry in the device may match a requested address with the stored addresses and generate logic signals that trigger activation of a repaired row in place of the defective row or column. Moreover, defective rows or columns that have been previously repaired once may be further repaired. To that end, logic circuitry implementing a trumping mechanism may be used to prevent activation of multiple data rows or columns for addresses that were repaired multiple times.

Post-packaging repair of redundant rows

An electronic device including: a fuse array including fuse cells organized along a first direction and a second direction, wherein each fuse cell includes: a fuse element configured to store information, and a selection circuit configured to provide access to the fuse element according to a position of the fuse cell element along the first direction and the second direction; and a fuse read circuit connected to the fuse array, the fuse read circuit configured to generate a fuse read output based on reading from one or more of the fuse cells simultaneously and in parallel.

A method of operating an electronic device includes: generating a fuse read output based on reading a fuse cell at a predetermined data location in a fuse array, wherein the predetermined data location is configured to store predetermined data pattern; comparing the fuse read output to the predetermined data pattern; and generating a read-enable trigger based on the fuse read output matching the predetermined data pattern, wherein the read-enable trigger is for reading content stored in the fuse array and for broadcasting the content to circuits within the electronic device.

Growing community of inventors

McKinney, TX, United States of America

John E Riley