Burroughs, Inc.

John E Legory

Kenneth Lindsay York

Peter R Annal

Daniel P Drogichen

Dana A Gryger

In a data processing system wherein a binary data message is protected by cyclic check codes, synchronization loss tolerance is incorporated by performing a binary transformation after encoding the message but prior to transmitting it or writing it to storage and by performing an inverse binary transformation upon receiving it or reading it from storage but prior to error checking. In one embodiment the transformation involves complementing a plurality of bits. In an alternate embodiment the transformation involves reversing the sequence of a plurality of contiguous bits.

Synchronization loss tolerant cyclic error checking method and apparatus

In a named data processing system, user ownership and verfication of data records is secured by assigning an unique record name to each data record, providing error checking covering both the data record and its associated record name, storing the data record, its associated record name and check code, and requiring the data record name to be provided in order to initiate a fetch operation. Further, the check code enables upon fetching, a verification that an incorrect data record was not inadvertantly fetched due to hardware or other failures. The association of a unique data name with each data record provides for self-descriptive data records thereby permitting the reconstruction of directories which describe the contents of various actual physical locations within an Input/Output system when such directions are lost or otherwise corrupted by hardware or other malfunctions.

Method and apparatus for enhancing I/O transfers in a named data

In a data processing error control system for named data, a parity check matrix and apparatus for using same provides for single error correcting of the data word and for multiple error detecting in both the data word and data name. The parity check matrix and apparatus utilize two additional parity check bits (over that required by a system using a prior art SEC/DED Hamming code) to provide protection against single bit errors, eight contiguous bit errors (i.e., hardware stuck at logical one or logical zero for the whole eight contiguous bits), similar four contiguous bit errors, and faults covering the entire data name field (which could occur, for example, if a wrong data word was fetched from memory). The parity check matrix is segmented and mated to the error correctional requirements and prevalent error modes of each field being protected. In encoding, parity check bits are generated for the combined data word and associated data name field. In decoding, an overall parity check of the check bits, data word and data name is performed for distinguishing between odd and even errors. Further, the parity check matrix is invoked to generate a parity checking number for addressing a decoding table circuit (realizable as a ROM) which in turn provides the error bit location for single bit correctable errors. Given the error bit location a correction circuit corrects (i.e., complements) the detected single erroneous bit in the data word or in the generated parity check bits.

Segmented error-correction system

An error control system for named data functions in a hierarchical memory system environment requiring only a single error-control encoding for each data word used therein. Each level of memory in the hierarchy thereof includes a data word storage device preceded by an error checking circuit to validate and correct when possible data to be stored therein. A translator operates upon the data name of the data word to be stored to indicate the area or portion of the storage device in which the data word is to be stored. A directory table associates data names with data word locations in the storage device, and a search mechanism fed by the translator searches the directory table in the area or portion so indicated for a data word location in the storage device to store the data word. If a data word is not located in one level of memory, the next lower level of memory is searched for same. Data words may be stored and translated or shifted through the various levels of memory without further error control encoding thereof. Fetching occurs in essentially the reverse manner of storing with the caveat that the single encloder used for storing is replaced by a decoder or error checking circuit.

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Paoli, PA, United States of America

John E Legory