Motorola Corporation

John E Hanna

Behrooz L Abdi

Ira G Miller

Eric Main

Alert amplifier (,) has a peak detector (,) and an operational amplifier (,) that dynamically set a bias voltage of a transducer (,) to minimize the standby current. In the absence of an input ring signal at an input terminal (,), the standby current in the transducer (,) is zero. The bias voltage to the transducer (,) is adjusted from a reference voltage downward in accordance with the input ring signal to minimize the current in the transducer (,) during the activation of the alert amplifier (,).

Integrated circuit amplifier and method of adaptive offset

A high precision DAC (10) incorporates a low precision DAC (18) and current sources (15(A)-15(O)) whose full-scale currents are adjusted to match a reference current generated by an analog calibration circuit (28). An additional low precision DAC (20) and another current source (16) are spares that allow periodic calibration of the high precision DAC (10) to occur in the background without taking the high precision DAC (10) off-line or out of service. A thermometer code generated by a thermometer code circuit (12) is used by a thermometer mapper circuit (13) to enable the most recently calibrated current sources to generate currents having the highest probability for use by the high precision DAC (10).

Circuit and method for calibrating a digital-to-analog converter

A real-time tracking filter circuit (10) that exhibits accurate zero placement is implemented in a monolithic structure by incorporating a three-input summing circuit (24) and a two-input summing circuit (28). The input signal (12) and a feedback signal (30) are summed and converted to a first current. The first current is integrated for providing a first integrated voltage (18). The first integrated voltage and an amplified input signal (40) and the feedback signal are summed and converted to a second current. The second current is integrated for providing a second integrated voltage as the feedback signal. The second integrated voltage and the amplified input signal are summed for providing the filtered output signal (36). Integration capacitors (20, 32) are grounded to remove parasitic effects that impact the pole-zero frequency response of the tracking filter output.

Circuit and method of zero generation in a real-time filter

An offset cancellation circuit corrects DC offset appearing at the input of a comparator circuit. The first input of a summing junction receives an input signal containing DC offset. The output of the summing junction drives the input of the comparator and a feedback amplifier, the latter of which returns to the second input of the summing junction. Any DC offset is processed through the feedback amplifier where it subtracts from the input signal for providing zero DC offset at the input of the comparator.

Offset cancellation circuit and method of reducing pulse pairing

A differentiator circuit is provided with a subtracter circuit connected to the input and output of the final stage of a main signal processing filter, the latter of which processes an input signal for providing a filtered output signal. The difference between the input and output signals of the final stage of the main signal processing filter provides a differentiated output signal having the same natural frequency and damping factor as the filtered output signal.

Circuit and method of signal differentiation

A current amplifier provides high gain and low output voltage. Differential input currents of the current amplifier are sunk by first and second transistors through a first resistor network. Any common mode variation in the input currents is detected by first and second emitter-follower transistors which control the bases of the first and second transistors, respectively, through a resistor divider network such that the first and second transistors conduct the common mode variation in the input currents and maintain the average value of the output voltages of the emitter-follower transistors substantially constant. An output differential amplifier is also responsive to the voltage difference between the emitter-follower transistors and the center tap of the resistor divider for providing constant output currents. The emitters of the output differential transistors return to ground through a second resistor network which enables the output voltage of the current amplifier to operate at a low value.

High gain differential current amplifier having a low output voltage

An integrated filter having a controllable frequency response includes a pair of cascaded differential transconductance amplifiers with the differential outputs of the first one of the pair being coupled to the differential inputs of the second one via coupling resistors and the differential inputs of the first one being coupled to inputs of the filter via input coupling resistors. The differential outputs of the second transconductance amplifier are coupled both to outputs of the filter and are fed back to the respective differential inputs of the two amplifiers to provide multiple inputs such that the damping factor of the filter is controllable for adjusting the filter frequency transfer function by varying the ratio of the coupling resistor value to the feedback resistor value while the damping factor is independent of the natural resonant frequency of the filter. Series coupled integrating capacitors are coupled across the differential outputs of both pairs of amplifiers with the interconnection therebetween return to ground.

Integrated filter circuit

A deglitch circuit for suppressing transient signals that appear at an output node includes a bias circuit for providing a bias signal; a transistor having its collector-emitter conduction path coupled in series to the output node and having a base coupled to the bias signal; and a capacitive element coupled between the output node and the base of the transistor for rendering the transistor conductive in response to a transient signal such that a low impedance circuit path is presented to the transient signal.

Low power transient suppressor circuit

A filter cell having common mode compensation for use in a differential integrating filter includes a transconductance amplifier that comprises a pair of differentially connected transistors the bases of which are coupled to respective inputs of the filter cell and whose emitters are interconnected to a current sinking transistor while the collectors are coupled via respective output circuitry to first and second outputs of the filter cell. Circuitry is provided to set the common voltage levels at the first and second outputs of the comprising a pair of resistors commonly connected at a circuit node that is a virtual ground for differential signals and the first and second filter cell outputs respectively. The circuit node is also coupled to the base of the current sinking transistor to thereby for a common mode closed loop in conjunction with a current supply that is also coupled to the circuit node. Common mode compensation to inhibit loop instability is provided by a pair of capacitors coupled in series between the collectors of differentially connected transistors and having the junction therebetween connected to the base of the current sinking transistor.

Common mode compensation for differential integrating filter

A current mirror provides an output current that is scaled in magnitude with respect to an applied input current includes first and second current turnaround circuits and circuitry coupled between the two current turnaround circuits which is responsive to the first current turnaround circuit for sourcing a current to the second current turnaround circuit the magnitude of which is scaled with respect to the input current that is sourced to the first current turn around circuit.

Current mirror have large current scaling factor

A circuit is disclosed for establishing a regulated negative voltage at an output which comprises first and second power supply conductors to which are supplied a positive DC operating potential and ground potential respectively, a push-pull driver circuit coupled between the two power supply conductors which is responsive to an applied switching signal for alternately sourcing and sinking current at an output thereof, circuitry coupled to the push-pull driver circuit for clamping the voltage level at the output of the latter to a predetermined value when current is source at the output of the push-pull driver circuit, a first capacitor coupled between the output of the push-pull circuit and a first terminal, a second capacitor coupled between second and third terminals with the second terminal being coupled to the output of the converter circuit and the third terminal being coupled to ground potential, and diode circuitry for alternately providing charging paths for the first and second capacitors between the output of the push-pull driver circuit and ground potential to produce the regulated negative DC voltage as charge is transferred between the first and second capacitors.

DC to DC converter

A low voltage clamp circuit comprises a transistor and semiconductor junction impedance circuitry for establishing an impedance such that the magnitude of a voltage applied across the emitter and collector of the transistor is clamped at a value that is less than the reverse breakdown voltage of the collector-to-emitter of the transistor if its base is shorted to the collector. The clamp circuit is suited to be manufactured in monolithic integrated circuit form and can be used to protect integrated bipolar transistors from having the reverse breakdown voltage of their emitter-base junctions exceeded.

Low voltage clamp

A comparator cell for analog-to-digital flash converters is provided that reduces power dissipation and peak voltage drop across a load while improving accuracy. An even number of level sensors are coupled to receive an analog input signal and provide a first and a second current. Each level sensor is biased by a different reference voltage. Means for receiving the first and second current and providing an output is coupled between the level sensors and a pair of load resistors. The load resistors are manufactured in a predetermined resistance ratio depending on the number of level sensors.

Comparator cell for analog-to-digital flash converter

A 'D' flip-flop circuit is disclosed which includes a master latch having data input transistors coupled to the input terminals thereof and data transfer transistors connected to the output thereof. A slave latch is connected to the output terminals of the data transfer transistors. The flip-flop circuit utilizes a resistive feedback network coupled between the emitter terminals of the transistors of the master latch to facilitate increased output voltages and stable predictable operating conditions. The data input transistors are connected as emitter follower circuits for driving the master latch transistors in a common base configuration for maximizing the speed-power product of the circuit.

'D' Flip-flop

A temperature compensated low voltage reference that produces an output voltage less than the silicon band-gap voltage. The low voltage reference includes at least a first and a second transistor for providing a voltage independent of variations in the collector power supply and at least a third transistor for developing a voltage that is a fractional value of the base-to-emitter voltage drop of a transistor. The at least a third transistor for developing is coupled with the at least a first and a second transistor for providing. The low voltage reference also includes an output transistor for providing an output voltage. The output transistor is controlled by the voltage provided by the at least a first and a second transistor for providing so that the output voltage is essentially insensitive to temperature variations and is a lower value than the silicon band-gap voltage.

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Mesa, AZ, United States of America

John E Hanna