International Business Machines Corporation

John E Gersbach

Ilya I Novof

Frank David Ferraiolo

Charles Joseph Masenas

Masayuki Hayashi

Wilbur David Pricer

Joseph Kinman Lee

Anthony Richard Bonaccio

Paul Wingshing Chung

Peter Edwin Cottrell

Edward J Nowak

Wendell P Noble

John Atkinson Fifield

Norman Jay Rohrer

Russell J Houghton

Charles R Hoffman

Badih El-Kareh

John Stanley Bialas, Jr

Bac V Pham

Charles K Erdelyi

Todd Williams

Sharon Lynne Von Bruns

Karl R Hense

Christian J Goetschel

John J Moser, Jr

Bruce W Singer

David W Blum

Charles R London

Shujaat Nadeem

Ick W Kim

Pete Granata

Ilya J Novof

Adolf M Zehle

A switched capacitor current reference circuit with improved tolerance. Additional optional devices maintain an output in the absence or loss of an input frequency.

CVF current reference with standby mode

A noise limited, video, digital to analog converter having an output transition time control with multiple discrete transition times. This is accomplished by a DAC control circuit in which the slew rate of the current is controlled by providing set current levels in the inverters that drive the DAC output current switches thus limiting the current available for charging and discharging the capacitance on the nodes which control the output signal. Additional control is provided by voltage clamping of these nodes which reduces the input voltage to the analog output and results in a cleaner output waveform. By so regulating and controlling the charging and discharging of these nodes, the variations in operation of the circuit due to the process used to produce the circuit in integrated form as well as temperature and supply voltage are further substantially reduced.

Slew rate control circuit

A voltage translation circuit translates an input signal having a first voltage level and a second voltage level to an output signal having the second voltage level and a third voltage level respectively. The voltage translation circuit according to the present invention includes a regenerative circuit having a first terminal and a second terminal. The voltage level at the first terminal increases responsive to the voltage level at the second terminal decreasing. The voltage level at the second terminal increases responsive to the voltage level at the first terminal decreasing. The voltage level at the first terminal defines the output signal. A first switch is coupled to the first terminal of said regenerative circuit, such that closing the first switch decreases the voltage level at the first terminal. A second switch is coupled to the second terminal of said regenerative circuit, such that closing the second switch decreases the voltage level at the second terminal.

Low power voltage translation circuit

According to the preferred embodiment of the present invention pull-up/pull-down circuits are provided that use transistors with different threshold voltages to assure power-up to the correct predetermined state. These circuits have the ability to hold a node up or down while drawing very little DC current. In one embodiment a pull-up/pull-down circuit is provided that powers up to a first state with the pull-up node high and the pull-down node low, and that can be toggled from one state to another. A second embodiment provides a pull-up or pull-down circuit that powers up to the desired state and can be disabled by pulling the pull-up node low or pulling the pull-down node high. The circuits remain disabled until the power to the circuit is cycled.

Pull-up and pull-down circuits

Temperatures on a chip, including particular regions of a chip are monitored by sensing changes in sub-threshold conduction of a field effect transistor (FET) integrated on the chip due to changes in charge carrier population distribution with temperature therein. Such changes in sub-threshold current with temperature are preferably detected using a current mirror and two FETs with different channel geometry and slightly different gate voltages such that the currents are equal at a specific design temperature. The slightly different gate voltages are conveniently provided by a low current voltage divider with or without on-chip voltage regulation in which resistor ratios can be accurately and repeatably obtained. Variations from that temperature thus yield large current differences and substantial signal swing which improve noise immunity. Hysteresis can be applied to the output (or amplified output) of the current mirror to obtain bistable thermostat-like action. Variant applications provide sensing at plural chip locations (e.g. for sensing temperature gradients and temperatures of autonomously operating portions of the chip) and a plurality of temperatures on the chip. Temperatures thus monitored control implementation of performance enhancing algorithms in regard to the chip.

On-chip thermometry for control of chip operating temperature

A self-timed circuit for use a clocked logic system is disclosed that comprises a timing detection device for detecting a timing margin of a critical path, the critical path being a path that limits the speed of the system. The circuit further comprises increase logic for increasing the speed of the system clock if the timing margin allows it, and decrease logic for decreasing the speed of the system clock if the timing margin indicates such a need. The increase and decrease logic comprise threshold generator and reset logic, and clock control logic.

Self-timed circuit having critical path timing detection

According to the preferred embodiment, a phase-locked loop system is provided that overcomes the limitations of the prior art by providing the ability to switch output frequencies without a disruption in the phase lock of the output signal. The system uses a first phase-locked loop coupled with a second phase lock-loop such that their output signals are phase aligned and a switching mechanism for switching between the first phase lock output signal and the second phase lock loop output signal. The system is thus able to switch the frequency of its output without a disruption in the phase-lock of the signal.

Variable-speed phase-locked loop system with on-the-fly switching and

A delay equalization circuit for minimizing the static phase error in a PLL is provided. The delay equalization circuit includes an external clock signal variable delay path, and an element for creating a pulse with a width proportional to the delay of the external clock signal variable delay path. The delay equalization circuit also includes a delay path in the feedback loop, and second element for creating a second pulse in proportion to the delay of the internal delay path. Finally, the circuit contains a comparison device. The comparison device compares the first and second pulses. The comparison device outputs a difference signal in proportion to the difference in the external and internal path delays. That difference signal is fed back and used to control the external path delay such that the external delay is driven to be substantially equal to the internal delay, minimizing the static phase error of the PLL device.

Delay equalization apparatus and method

According to the preferred embodiment of the present invention, a phase-locked loop is provided that overcomes the limitations of the prior art by facilitating fast locking on transition to a different output frequency. The phase-locked loop comprises an oscillator that provides a phase-locked loop output signal at various selected frequencies; a feedback divider; a phase comparator; a memory storage mechanism for storing phase-locked loop control information corresponding to selected output frequencies; and a digital circuit mechanism that receives the control information from the memory storage mechanism on transition to a different output frequency. The control information includes a digital counter value corresponding to the last recorded phase difference of the output signal at the different output frequency. On transition, this information is loaded directly to the digital circuit mechanism, reducing the need and time required for the phase comparator operation to drive the PLL to lock. Thus, the phase-locked loop can quickly achieve phase lock at the different operating frequency.

Fast locking variable frequency phase-locked loop

A variable frequency oscillator circuit includes a ring oscillator circuit, a plurality of adjustment means for adjusting an output frequency of the ring oscillator circuit, at least one of the adjustment means having monotonic behavior, adapted to switch between first adjustment levels at a first rate and at least one of the adjustment means having non-monotonic behavior, adapted to switch between second adjustment levels at a second rate which is less than the first rate, such that the means having monotonic behavior adjusts for monotonicity errors which occur during switching.

Digitally controlled oscillator circuit

A sensing amplifier that works over a large operating frequency having a plurality of reference inputs, at least one signal input and at least one signal output, where the amplifier comprises a plurality of transistors to internally compare the signal input to the average value of the reference inputs and producing an output based on the comparison. In some cases, the output can be a latched binary signal.

Multiple reference sense amplifier

According to the preferred embodiment, an improved feedforward path is provided that improves the frequency response and reduces the output jitter of a phase-locked loop. Specifically, the frequency response is improved by providing a zero in the frequency response of the phase-locked loop by means of a feedforward path. The feedforward path delivers a feedforward charge to the oscillator of the phase-locked loop. According to the preferred embodiment, the feedforward path reorders the feedforward charge, such that the feedforward charge is stored and distributed equally across all the phase-locked loop output signal sub-cycles.

Phase-locked loop with charge distribution

A protective circuit for a phase lock loop ensures that the VCO does not initiate a runaway condition when outputting a signal having a frequency higher than the feedback divider can respond to. During normal phase lock operation, a counter keeps track of the PLL input signal and is reset by the feedback divider. In the runaway condition the counter is not reset and triggers a control signal to the VCO. A second counter can be used to keep track of the feedback divider output and to reset the first counter. When the first counter far outruns the second counter the control signal is triggered.

Anti-latching mechanism for phase lock loops

A circuit for delivering an accurate reference current independent of operating frequency that is implementable on-chip and that is relatively insensitive to process and temperature variations. A frequency source controls a rate of charge transfer via a switched capacitor to generate a constant current over different frequencies. A complimentary doped FET provides a band gap voltage imposed over a known resistance to generate the output current.

Band gap current reference circuit

A switched capacitor, integrated circuit employing at least one non-linear capacitor charged and discharged in response to a reference frequency includes a first conductive device for charging the non-linear capacitor to the supply voltage in response to one polarity of the reference frequency, and a second conductive device for discharging the non-linear capacitor in response to the opposite polarity of the reference frequency to a voltage level opposite that of the voltage source minus the threshold voltage of a third conductive device in the discharge path. Preferably, a pair of non-linear capacitors are employed, each being charged on alternate half cycles of the reference frequency, and the non-linear capacitors are accumulator capacitors. The circuit also include means for rapidly initiating the charging and discharging of said capacitors and for precluding changes in the state of charge or discharge thereof due to parasitic diodes in the circuit.

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Burlington, VT, United States of America

John E Gersbach