Oracle International Corporation

Oracle America, Inc.

Sun Microsystems, Inc.

Other

Kotura, Inc.

Axalume, Inc.

Alternate Fuels, Inc.

Oracle America, Inc. Formerly Known As Sun Microsystems, Inc.

John E Cunningham

Ashok V Krishnamoorthy

Xuezhe Zheng

Ivan Shubin

Hiren D Thacker

Guoliang Li

Ronald Ho

Robert J Drost

James G Mitchell

Brian Walter O'Krafka

Kannan Raj

Jin Yao

Stevan S Djordjevic

Ying Luo

Shiyun Lin

Robert David Hopkins, Ii

Jon Lexau

Mehdi Asghari

Dazeng Feng

Jing Shi

Ilya A Sharapov

Eugene Michael Chow

Howard Lee Davidson

Pranay Koka

Bruce M Guenin

Roshanak Shafiiha

Daniel C Lee

Xuehze Zheng

David K McElfresh

Wei Qian

Frankie Liu

Anders Landin

Michael Oliver McCracken

Shirong Liao

Chaoqi Zhang

Edward Lee Follmer

Jingqiong Xie

Jeffrey W Denq

Roland E Goodenough

Hyung Suk Yang

Craig A Stephen

Brian W O'KRAFKA

A high-power packaged laser array that is thermal reflow compatible is described. Notably, a high-power III-V laser array is integrated on a silicon substrate with a matching array of ball lenses, an isolator and a coupler (such as a reflective layer) to achieve an edge-coupled or a surface-normal output laser array. In some embodiments, an isolator with a permanent magnet is used to preserve the magnetic domain or state of the isolator during the thermal reflow(s), which can involve temperatures up to 250 C. In order to relax the misalignment tolerance when integrating with the silicon chip, a laser array with a larger optical mode may be used to increase the output beam size. Moreover, a III-V laser array with an angled output optical waveguide can be used to improve the stability of the lasers at high power.

High-power packaged laser array

An optical receiver includes: an active transimpedance amplifier (TIA) that converts a photocurrent from a photosensor into an active voltage signal; a high-speed amplifier that amplifies the active voltage signal to produce an amplified voltage signal that comprises an output for the optical receiver; and a reference-voltage-generation circuit that generates a reference voltage for the high-speed amplifier. This reference-voltage-generation circuit includes a dummy TIA that is identical to the active TIA, but does not receive a live input signal, and produces a dummy voltage signal. It also includes a low-speed amplifier which includes: an active input that receives the active voltage signal from the active TIA output; a dummy input that receives the dummy voltage signal from the dummy TIA output; and an output that controls directly or indirectly the reference voltage for the high-speed amplifier. In the direct control case, the output of low-speed amplifier includes a feedback connection that feeds back into the dummy input. In the indirect control case, the output of low-speed amplifier adjusts the reference voltage for the high-speed amplifier through dummy TIA internal biasing.

Extracting an embedded DC signal to provide a reference voltage for an optical receiver

A photonic integrated circuit (PIC) is described. This PIC includes an inverse facet mirror on a silicon optical waveguide for optical proximity coupling between two silicon-on-insulator (SOI) chips placed face to face. Accurate mirror facets may be fabricated in etch pits using a silicon micro-machining technique, with wet etching of the silicon &#x3c;110&#x3e; facet at an angle of 45&#xb0; when etched through the &#x3c;100&#x3e; surface. Moreover, by filling the etch pit with polycrystalline silicon or another filling material that has an index of refraction similar to silicon (such as a silicon-germanium alloy), a reflecting mirror with an accurate angle can be formed at the end of the silicon optical waveguide using: a metal coating, a dielectric coating, thermal oxidation, or selective silicon dry etching removal of one side of the etch pit to define a cavity.

Surface-normal coupler for silicon-on-insulator platforms

A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are proximate to each other in the chip package. The integrated circuit includes electrical circuits that modulate data, communicate data, and serialize/deserialize data, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a top surface of an interposer, and a top surface of the integrated circuit is electrically coupled to a front surface of the optical integrated circuit. Furthermore, a bottom surface of the optical integrated circuit faces the top surface of the interposer, and the front surface of the optical integrated circuit is optically coupled to an optical-fiber receptacle, which in turn is optically coupled to an optical-fiber connector.

Packaged opto-electronic module

Embodiments of a system that includes an array of chip modules (CMs) is described. In this system, a given CM in the array includes a semiconductor die that is configured to communicate data signals with one or more adjacent CMs through electromagnetic proximity communication using proximity connectors. Note that the proximity connectors are proximate to a surface of the semiconductor die. Moreover, the given CM is configured to communicate optical signals with other CMs through an optical signal path using optical communication, and the optical signals are encoded using wavelength-division multiplexing (WDM).

Wavelength-division multiplexing for use in multi-chip systems

A photonic integrated circuit (PIC) is described. This PIC includes a semiconductor-barrier layer-semiconductor diode in an optical waveguide that conveys an optical signal, where the barrier layer is an oxide or a high-k material. Moreover, semiconductor layers in the semiconductor-barrier layer-semiconductor diode may include geometric features (such as a periodic pattern of holes or trenches) that create a lattice-shifted photonic crystal optical waveguide having a group velocity of light that is lower than the group velocity of light in the first semiconductor layer and the second semiconductor layer without the geometric features. The optical waveguide is included in an optical modulator, such as a Mach-Zehnder interferometer (MZI).

Enhanced optical modulation using slow light

A photonic integrated circuit (PIC) is described. This PIC includes a grating coupler for surface-normal coupling that has an alternating pattern of grating teeth and grating trenches, where the grating trenches are filled with an electro-optical material. By applying an electric potential to the grating teeth, the index of refraction of the electro-optical material can be modified.

Tunable silicon grating couplers

An electro-refraction modulator includes a series of layers with different doping levels surrounding a single-crystal regrown p-n junction implemented in a silicon-on-insulator (SOI) technology. The regrown p-n junction is spatially abrupt and precisely defined, which significantly increases the tuning efficiency of the electro-refraction modulator while maintaining acceptable insertion loss. Consequently, the electro-refraction modulator (such as a resonator modulator or a Mach-Zehnder interferometer modulator) can have high bandwidth, compact size and reduced drive voltage. The improved performance of the electro-refraction modulator may facilitate silicon-photonic links for use in applications such as wavelength-division multiplexing.

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An optical device is described. This optical device includes optical components having resonance wavelengths that match target values with a predefined accuracy (such as 0.1 nm) and with a predefined time stability (such as permanent or an infinite time stability) without thermal tuning and/or electronic tuning. The stable, accurate resonance wavelengths may be achieved using a wafer-scale, single (sub-second) shot trimming technique that permanently corrects the phase errors induced by material variations and fabrication inaccuracies in the optical components (and, more generally, resonant silicon-photonic optical components). In particular, the trimming technique may use photolithographic exposure of the optical components on the wafer in parallel, with time-modulation for each individual optical component based on active-element control. Note that the physical mechanism in the trimming technique may involve superficial room-temperature oxidation of the silicon surface, which is induced by deep-ultraviolet radiation in the presence of oxygen.

Single shot correction of resonant optical components

An integrated circuit is described. This integrated circuit includes a ferroelectric layer disposed on top of the ring resonator, which has a resonance wavelength. The ferroelectric layer is positioned between electrical contacts. Moreover, there may be amorphous semiconductor materials between the electrical contacts and the ferroelectric layer. For example, the amorphous semiconductor materials may include: p-type amorphous silicon and/or n-type amorphous silicon. By applying a reverse-bias voltage across the electrical contacts, an electric field is generated in a plane approximately parallel to a top surface of the ring resonator. This electric field electro-optically tunes the resonance wavelength. The ring resonator may operate at low voltage and can be integrated with a silicon optical waveguide on a silicon-on-insulator (SOI) platform.

Ferroelectric-enhanced tuning of ring resonators by using fields parallel to and above a top surface thereof

An integrated optical device includes an electro-absorption modulator disposed on a top surface of an optical waveguide. The electro-absorption modulator includes germanium disposed in a cavity between an n-type doped silicon sidewall and a p-type doped silicon sidewall. By applying a voltage between the n-type doped silicon sidewall and the p-type doped silicon sidewall, an electric field can be generated in a plane of the optical waveguide, but perpendicular to a propagation direction of the optical signal. This electric field shifts a band gap of the germanium, thereby modulating the optical signal.

Integrated electro-absorption modulator

A hybrid optical source includes a substrate with an optical amplifier (such as a III-V semiconductor optical amplifier). The substrate is coupled at an angle (such as an angle between 0 and 90&#xb0;) to a silicon-on-insulator chip. In particular, the substrate may be optically coupled to the silicon-on-insulator chip by an optical coupler (such as a diffraction grating or a mirror) that efficiently couples (i.e., with low optical loss) an optical signal into a sub-micron silicon-on-insulator optical waveguide. Moreover, the silicon-on-insulator optical waveguide optically couples the light to a reflector to complete the hybrid optical source.

Vertical integration of a hybrid optical source

A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are proximate to each other in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. Moreover, a front surface of the integrated circuit is electrically coupled to a top surface of an interposer, and this top surface is in turn electrically coupled to a front surface of an input/output (I/O) integrated circuit that faces the top surface. Furthermore, the front surface of the I/O integrated circuit is electrically coupled to a top surface of the optical integrated circuit, where the top surface of the optical integrated circuit faces the front surface of the I/O integrated circuit.

Hybrid-integrated photonic chip package with an interposer

A multi-level interposer plate and a multi-chip module (MCM) that includes the multi-level interposer plate are described. First surfaces and second surfaces in different regions of the multi-level interposer plate have associated, different thicknesses. Moreover, first micro-spring connectors and second micro-spring connectors are respectively disposed on the first surfaces and the second surfaces. In the MCM, a given one of the first surfaces of the multi-level interposer plate faces a bridge chip in a first layer in an array of chips in the MCM so that first connectors, disposed on the bridge chip, mechanically and electrically couple to the first micro-spring connectors. Similarly, a given one of the second surfaces of the multi-level interposer plate faces an island chip in a second layer in the array of chips so that second connectors, disposed on the island chip, mechanically and electrically couple to the second micro-spring connectors.

Method for fabricating multi-chip module with multi-level interposer

A chip package includes an optical integrated circuit (such as a hybrid integrated circuit) and an integrated circuit that are adjacent to each other on the same side of a substrate in the chip package. The integrated circuit includes electrical circuits, such as memory or a processor, and the optical integrated circuit communicates optical signals with very high bandwidth. In addition, an input/output (I/O) integrated circuit is coupled to the optical integrated circuit between the substrate and the optical integrated circuit. This I/O integrated circuit includes high-speed I/O circuits and energy-efficient driver and receiver circuits and communicates with optical devices on the optical integrated circuit. By integrating the optical integrated circuit, the integrated circuit and the I/O integrated circuit in close proximity, the chip package may facilitate improved performance compared to chip packages with electrical interconnects.

Hybrid integrated photonic chip package

Growing community of inventors

San Diego, CA, United States of America

John E Cunningham