Texas Instruments Corporation

John E Campbell

Shawn T Walsh

James B Friedmann

Gregory Boyd Shinn

Sue E Crank

Joe G Tran

Michelle L Hartsell

Ju-Ai Ruan

Wayne A Bather

Troy A Yocum

Byron T Ahlburn

Jaideep Mavoori

Somit Joshi

Thomas M Parrill

Der'E Jan

Janice D Makos

Joshua J Robbins

Arun Sivasothy

Michael J McGranaghan

A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.

Shallow trench isolation planarization using self aligned isotropic etch

A method is given for removing excess oxide from active areas after shallow trench isolation, without the use of chemical-mechanical polishing. A nitride mask protects active areas during the etch of isolation trenches. The trenches are filled with oxide, using high density plasma deposition, which simultaneously etches, providing a sloping contour around the isolation trenches. A further layer of nitride is used to provide a cap over the trench which seals to the underlying layer of nitride. The cap layer of nitride receives a patterned etch to remove the cap only over the active areas. This allows a selective etch to remove the excess oxide, which can be followed by a selective etch to remove the nitride layers.

Method for trench isolation of semiconductor devices

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Plano, TX, United States of America

John E Campbell