International Business Machines Corporation

John E Campbell

William T Devine

Kris V Srikrishnan

Michael James Chan

Steven F Hajek

Sebastian Theodore Ventrone

Randall J Easter

Vincent A Spano

Paul L Wiltgen

Myron W Zajac

Kevin Charles Gower

Gerhard Robert Thompson

Charles H Milligan

William F Washburn

Roy A Wood

Frank A Almquist

Cyril A Price

George A Williams, Ii

Andrew M Simon

John F Larsen

Stephen W Flaherty

David F Anderson

A system and method for improving the efficiency of an object-level instruction stream in a computer processor. Translation logic for generating translated instructions from an object-level instruction stream in a RISC-architected computer processor, and an execution unit which executes the translated instructions, are integrated into the processor. The translation logic combines the functions of a plurality of the object-level instructions into a single translated instruction which can be dispatched to a single execution unit as compared with the untranslated instructions, which would otherwise be serially dispatched to separate execution units. Processor throughput is thereby increased since the number of instructions which can be dispatched per cycle is extended.

Dynamic object-level code translation for improved performance of a computer processor

A method for capturing data includes receiving a plurality of external clock signals including a first external clock signal and a second external clock signal. Each external clock signal has a first frequency, a first edge and a second edge. Data is received on one or more signal links at a second frequency that is faster than the first frequency. The data includes consecutive data with a first data signal followed by a second consecutive data signal. The consecutive data is captured at the second frequency in response to the first edges and not the second edges of the external clock signals. The first data signal is captured based on the first edge of the first external clock signal and the second consecutive data signal is captured based on the first edge of the second external clock signal.

Systems, methods and computer program products for high speed data transfer using a plurality of external clock signals

A memory system including a first memory subsystem having a buffer device with a first port and a second port, one or more memory devices coupled to the buffer device via the second port, and a first two-on-one link for coupling to a memory controller for providing communication between the buffer device and the memory controller. The first two-on-one link is coupled to the first port of the buffer device. The first memory subsystem is configured to transfer data between at least one memory device of the one or more memory devices and the memory controller via the buffer device. The first two-on-one link includes up to two transceivers connected to a single link, with at least one of the up to two transceivers consisting of any one of two or more transmitters for transmitting signals or two or more receivers for receiving signals.

Memory system including a two-on-one link memory subsystem interconnection

Systems, methods and computer program products for capturing data. The methods include receiving an external clock signal having a first frequency, a first edge and a second edge. A clock period of the external clock period is the amount of time between any two successive first edges. The external clock signal is transformed into an internal clock signal based on the first edge and not the second edge of the external clock signal. Parallel data is received on a first plurality of signal links. The parallel data is received at a second frequency that is faster than the first frequency. The parallel data is captured using the internal clock signal.

Systems, methods and computer program products for high speed data transfer using an external clock signal

A method is provided in which for fabricating a complementary metal oxide semiconductor (CMOS) circuit on a semiconductor-on-insulator (SOI) substrate. A plurality of field effect transistors (FETs) are formed, each having a channel region disposed in a common device layer within a single-crystal semiconductor layer of an SOI substrate. A gate of the first FET overlies an upper surface of the common device layer, and a gate of the second FET underlies a lower surface of the common device layer remote from the upper surface. The first and second FETs share a common diffusion region disposed in the common device layer and are conductively interconnected by the common diffusion region. The common diffusion region is operable as at least one of a source region or a drain region of the first FET and is simultaneously operable as at least one of a source region or a drain region of the second FET.

Method and structure for buried circuits and devices

Dynamic object-level code transaction for improved performance of a computer

A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

A CMOS driver circuit minimizes a pass-through current flowing from a first voltage terminal to a second voltage terminal during transitions of an input signal. At least two transistors are connected in series between two voltage terminals. One transistor turns off when the input signal transitions from a low logic state to a high logic state. Another transistor turns off when the input signal transitions high-to-low. During either input signal transition, one of the transistors is off, thereby cutting the path between the voltage terminals to reduce or eliminate the pass-through current. The two transistors are controlled by the output of the circuit through a feedback loop. This feedback loop can include a delay element, one transistor controlled by a single synchronizing clock signal, or two transistors controlled by two complementary clock signals. The driver circuit can be used as a building block to provide conventional combination logic functions. Specific embodiments for an inverter and a NOR gate are described.

CMOS driver circuit for providing a logic function while reducing

A system is disclosed for selectively altering the functional characteristics of a data processing system without physical or mechanical manipulation by providing an access code from a remote personal identification number generator to a secure controller and store of the computer system. This enables remote authorization of change in function of the computer system, such as performance tune up, speeding clock time, changing function and like changes. The computer system is first manufactured having a predetermined set of functional characteristics. A multibit alterable code which includes a functional characteristic definition is then initially loaded into physically secure, nonvolatile memory within the data processing system, utilizing an existing bus, or a fusible link which may be opened after loading is complete. The functional characteristic definition is loaded from nonvolitile memory into a nonscannable register within a secure portion of a control logic circuit each time power is applied to the data processing system and the definition is then utilized to enable only selected functional characteristics. Alternate functional characteristics may thereafter be selectively enabled by entering a security code which matches one of a number of preloaded codes and an encoded alternate functional characteristic definition. The alternate functional characteristic definition may be enabled on a one-time, metered, or regularly scheduled basis and variable capability data processing systems may be implemented in this manner utilizing a single manufactured system, without the necessity of manufacturing and storing multiple data processing system models.

Self modifying access code for altering capabilities

A method and system are disclosed for selectively altering the functional characteristics of a data processing system without physical or mechanical manipulation. A data processing system is first manufactured having a predetermined set of functional characteristics. A multibit alterable code which includes a functional characteristic definition is then initially loaded into physically secure, nonvolatile memory within the data processing system, utilizing an existing bus, or a fusible link which may be opened after loading is complete. The functional characteristic definition is loaded from nonvolatile memory into a nonscannable register within a secure portion of a control logic circuit each time power is applied to the data processing system and the definition is then utilized to enable only selected functional characteristics. Alternate functional characteristics may thereafter be selectively enabled by entering a security code which matches one of a number of preloaded codes and an encoded alternate functional characteristic definition. The alternate functional characteristic definition may be enabled on a one-time, metered, or regularly scheduled basis and variable capability data processing systems may be implemented in this manner utilizing a single manufactured system, without the necessity of manufacturing and storing multiple data processing system models.

Method and system for selectively altering data processing system

Methods and apparatus are provided for electronically configuring hardware features and options. A computer chip encoding method is provided in which a predetermined code or encryption sequence is uniquely associated with a computer chip. This code is used to modify a hardware configuration by enabling new features or options. The systems and methods reduce manufacturing and inventory costs by allowing a generic product to be produced which is then customized to meet the needs of the user. In addition, features and options of a data processing system can be dynamically upgraded without interruption of service or hardware replacement.

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Wappingers Falls, NY, United States of America

John E Campbell