Digital Equipment Corporation

John E Buzynski

Robert E Stewart

William D Strecker

David Thompson

Robert Giggi

An arbitration technique for controlling access to a bit-serial bus by multiple nodes in a data processing network. Upon detection of no carrier on the bus (56), a node desiring access to the bus waits a predetermined number of quiet slots (60, 64), each slot being a predetermined interval. If that period elapses without another node's carrier being detected (64), the node desiring access is permitted to transmit (64, 68). For each node, two such delay-interval possibilities are provided, one high slot count (and, hence, low priority) and one low slot count (and, hence, high priority). The delay-interval selection for a node is switched from time to time on a round-robin basis so that all nodes get equal average priority. The high value of the delay interval is N+M+1 slots, where N is the node number and M is the maximum number of nodes allowed on the bus; the low value is N+1 slots. Initially, each node uses the former value. Upon unsuccessful contention for the bus, the delay-interval selection used next by the node depends on the number, LW, of the node which last won access to the bus. Upon detecting a carrier while waiting for access to the bus (i.e., losing arbitration to a higher-priority node), the node which is waiting for the bus compares its node number N to the number LW of the node which started transmitting (58). If LW was less than N, the node waiting for access uses a new waiting time of N+1 slots the next time the delay interval begins (62A); if LW was greater than N, the new delay interval value is N+M+1 slots (62B).

Dual-count, round-robin distributed arbitration technique for serial

An interface circuit (10) for coupling a parallel data device (12) to a serial data channel (14, 16) over which Manchester-type codes are transmitted. In the interface circuit, an efficient and reliable Manchester decoder (22), comprising a flip-flop (50), an exclusive-or gate (52), and at least one delay line (58A or 58B) separates the data and clocking signals. The serial data signals are clocked into a serial register (30) under control of the external clocking signals from the channel. A carrier detector (24) enables the serial register only when valid information signals are present. A parallel data register (40) receives in parallel the data from the serial data register. To get in phase the external clocking signals with the internal clock source, an internal clock synchronizing circuit (34, 42) recycles the internal clock source upon the occurrence of a synchronizing character that is transmitted over the serial data channel. In this fashion, the internal operations of the parallel data transfers are in phase, but isolated from the external clocking signals so that in the event that the external clocking signals become corrupted due to noise or simultaneous transmissions of information signals by different devices, the internal parallel transfer operations may continue freely without disruption.

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Windham, NH, United States of America

John E Buzynski