International Business Machines Corporation

John E Barwin, Iii

Harold Pilo

Jeanne P S Bickford

Amol Anil Joshi

Baozhen Li

Michael Richard Ouellette

Paul Steven Zuchowski

Leon Jacob Sigal

Brian A Worth

William John Livingstone

Steven Harley Lamphier

Jason Chung

A method of characterizing an electromigration (EM) parameter for use in an integrated circuit (IC) chip design including, inputting a layout of a wire layer and identifying a signal gate-circuit including electrically parallel paths, connected to an output of the signal gate from the layout. Based on widths for each of the paths, determining a maximum possible current for each of the paths, and calculating an average current for each of the paths. Identifying a path that is most limited in its current carrying capacity by possible EM failure mechanisms, and storing in a design library, a possible maximum current output to the identified limiting path, as the EM parameter.

Identifying and mitigating electromigration failures in signal nets of an integrated circuit chip design

A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design&#x2014;variable EM limit of each pre-defined circuit.

Method of managing electro migration in logic designs and design structure thereof

Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.

Integrated circuit design method and system

A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design-variable EM limit of each pre-defined circuit.

The invention provides for a method for architecting a delay locked loop clock signal comprising: providing at least one clock signal to a clock signal splitter; alternately outputting the at least one clock signal from the clock signal splitter on at least two matched delay lines; alternately propagating the clock signal down each of the at least two matched delay lines; specifying a delay period for each of the matched delay lines with a control signal; updating said the two matched delay lines with the control signal when a fixed update window is always present on the matched delay lines; and distributing the clock signal to synchronously update the at least two matched delay lines, wherein no transitions are present in the fixed update window on the matched delay lines. Collect clock pulse outputs from the delay lines and reconstruct a delayed version of the input clock.

Fully synchronous DLL with architected update window

Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.

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Essex Junction, VT, United States of America

John E Barwin, Iii