Aehr Test Systems, Inc.

John Dinh Hoang

Donald Paul Richmond, Ii

Jerzy Lobacz

Patrick M Shepherd

James F Tomic

William D Barraclough

Jeffrey A Brehm

Mikhail A Alperin

Jerry Lobacz

A burn-in and electrical test system () includes a temperature controlled zone () and a cool zone () separated by a transition zone. The temperature controlled zone () is configured to receive a plurality of wafer cartridges () and connect the cartridges () to test electronics () and power electronics (), which are mounted in the cool zone (). Each of the wafer cartridges () contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics () consists of a pattern generator PCB () and a signal driver and fault analysis PCB () connected together by a parallel bus (). The pattern generator PCB () and the fault analysis PCB () are connected to a rigid signal probe PCB () in cartridge () to provide a straight through signal path. The probe PCB () is rigid in order to allow close control of capacitance between each signal line and a backplane, thus providing impedance controlled interconnections between a semiconductor wafer under test and the test electronics (). The power distribution system () is connected to a probe power PCB () in the cartridge (). The probe power PCB () has at least a bendable portion in order to allow it to be positioned closely adjacent to and parallel with the rigid probe PCB (), yet extend a substantial distance away from the probe PCB () at its interconnection ().

Wafer level burn-in and electrical test system and method

A burn-in and electrical test system ( ) includes a temperature controlled zone ( ) and a cool zone ( ) separated by a transition zone The temperature controlled zone ( ) is configured to receive a plurality of wafer cartridges ( ) and connect the cartridges ( ) to test electronics ( ) and power electronics ( ), which are mounted in the cool zone ( ). Each of the wafer cartridges ( ) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics ( ) consists of a pattern generator PCB ( ) and a signal driver and fault analysis PCB ( ) connected together by a parallel bus ( ). The pattern generator PCB ( ) and the fault analysis PCB ( ) are connected to a rigid signal probe PCB ( ) in cartridge ( ) to provide a straight through signal path. The probe PCB ( ) is rigid in order to allow close control of capacitance between each signal line and a backplane, thus providing impedance controlled interconnections between a semiconductor wafer under test and the test electronics ( ). The power distribution system ( ) is connected to a probe power PCB ( ) in the cartridge ( ). The probe power PCB ( ) has at least a bendable portion in order to allow it to be positioned closely adjacent to and parallel with the rigid probe PCB ( ), yet extend a substantial distance away from the probe PCB ( ) at its interconnection ( ).

A high density interconnect system (30) employs contact fingers (32) on both surfaces (34) and (36) of burn-in PCB (38), feed-through PCB (40) and driver PCB (42). Each of the PCBs (38), (40) and (42) has a card-edge connector (44), (46) and (48). The feed-through PCB (40) has a second card-edge connector (40) and a second set of contact fingers (32), since it mates with both the burn-in PCB (38) and the driver PCB (42). The contact fingers (32) and the card-edge connectors (44), (46), (48) and (50) of each PCB (38), (40) and (42) mate inversely with each other on adjacent PCBs, i.e., the card-edge connector (44) of the burn-in PCB (38) mates with the contact fingers (32) of the feed-through PCB (40), and the card-edge connector (46) of the feed-through PCB (40) mates with the contact fingers (32) of the burn-in PCB (38), for example. The same relationship exists between the card-edge connector (50) of the feed-through PCB (40), the card-edge connector (48) of the driver PCB (42) and the contact fingers (32) of the feed-through PCB(40) and the driver PCB (42).

High-density interconnect technique

Growing community of inventors

San Jose, CA, United States of America

John Dinh Hoang