Adesto Technologies Corporation

Axon Technologies Corporation

John Dinh

Shane Charles Hollmer

Derric Lewis

Venkatesh P Gopinath

Nad Edward Gilbert

Juan Pablo Saenz Echeverry

Nathan Gonzales

Deepak Kamalanathan

Michael N Kozicki

Foroozan Sarah Koushan

John Ross Jameson

Narbeh Derhacobian

Stephen Trinh

Ming Sang Kwan

Gideon Intrater

Daniel Wang

Hendrik Hartono

Derric Jawaher Herman Lewis

Duong Vinh Hao

Nguyen Khac Hieu

Mark T Ramsbey

Jeffrey Allan Shields

Yi Ma

Bard Pedersen

Chakravarthy Gopalan

Michael Van Buskirk

Ishai Naveh

Janet Wang

John Ross Jameson, Iii

Ming Kwon

Vasudevan Gopalakrishnan

A memory device can include a nonvolatile memory (NVM) cell array, data path circuits, coupled between the NVM cell array and an output of the device, that are configured to enable access to the NVM cell array via a plurality of bit lines. A first charge pump can generate a first voltage supply. A second charge pump can generate a second voltage supply. Switch circuits are configured to, in a first mode, couple the first voltage supply to data path circuits, and in a second mode, couple the second voltage supply to the data path circuits. The first charge pump, the second charge pump, the switch circuits, the data path circuits and the NVM cell array are formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

Nonvolatile memory devices, systems and methods with switching charge pump architectures

A selection circuit includes: a first selection device coupled between a write IO line and a first node; a second selection device coupled between a read IO line and a second node; a third selection device controllable by a first address decode signal, and coupled between a first bit line and a third node; a fourth selection device controllable by a second address decode signal, and coupled between a second bit line and the third node; a first suppression device controllable by a write enable signal, and coupled between the second node and ground; a second suppression device controllable by a read enable signal, and coupled between the first node and ground; a first isolation device controllable by the write enable signal, and coupled between the first and third nodes; and a second isolation device controllable by the read enable signal, and coupled between the second and third nodes.

Memory device with adaptive noise and voltage suppression during read-while-write operations

A memory device can include a plurality of banks, each bank including a memory cell array of nonvolatile (NV) memory cells; a plurality of charge pumps, including a first charge pump and second charge pump; and a switch circuit. The switch circuit can be configured to, in a first mode, connect the first charge pump to first circuits of the banks and isolate the second charge pump from the first circuits, and in a second mode, isolate the first charge pump from the first circuits and connect the second charge pump to the first circuits.

A memory device can include a plurality of memory cells formed in a substrate, each having a resistive element programmable between at least two different resistance states, including memory cells configured to store data received by the memory device, and reference cells; a reference circuit formed in the substrate configured to generate at least a first reference resistance from resistances of a plurality of reference cells; a sense circuit formed in the substrate coupled to the memory cells and at least the first reference resistance and configured to compare a resistance of a selected memory cell to at least the first reference resistance to determine the data stored by the selected memory cell.

Reference circuits and methods for resistive memories

A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.

Ultra-deep power down mode control in a memory device

A method of controlling write parameter selection in a memory device, can include: (i) storing a configuration set number in a configuration register, where the configuration register is accessible by a user via an interface; (ii) receiving a write command from a host via the interface; (iii) comparing the stored configuration set number against set numbers in a register block to determine a match or a mismatch; (iv) downloading configuration bits from a memory array into the register block in response to the mismatch determination; (v) selecting a configuration set corresponding to the stored configuration set number from the register block in response to the match determination; and (vi) using the selected configuration set to perform a write operation on the memory device to execute the write command.

Write parameter switching in a memory device

A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, where the plurality of components comprises the command user interface; a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode; the memory device being operable to enter the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and the memory device being operable to exit the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command.

Memory device ultra-deep power-down mode exit control

In one embodiment, a method of operating a resistive switching device includes applying a signal comprising a pulse on a first terminal of a two terminal resistive switching device having the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period. The first time period is at least 0.1 times a total time period of the pulse.

Resistive memory device with ramp-up/ramp-down program/erase pulse

A circuit can include a signal section that includes a first signal transistor configured to operate in a subthreshold region to maintain the signal node at about VCC as VCC rises from a low level; a high threshold section that enables a current path from the signal node to the low power supply node only after a voltage at the detect node exceeds a level greater than a threshold voltage (Vt); and an output section having transistors with relatively long channels, for reduced crowbar current.

Circuits and systems having low power power-on-reset and/or brown out detection

In one embodiment, a semiconductor memory device includes a plurality of resistive switching memory cells, where each resistive switching memory cell can include: (i) a programmable impedance element having an anode and a cathode; (ii) an access transistor having a drain coupled to a bit line, a source coupled to the programmable impedance element cathode, and a gate coupled to a word line; (iii) a well having a first diffusion region configured as the source, a second diffusion region configured as the drain, and a third diffusion region configured as a well contact; and (iv) a diode having a cathode at the second diffusion region, and an anode at the third diffusion region, where the diode is turned on during an erase operation on the programmable impedance element.

Resistive switching memory having a resistor, diode, and switch memory cell

A memory device can include a plurality of memory cells formed over a substrate, each memory cell including a tunnel access device that enables current flow in at least one direction predominantly due to tunneling, and a storage element programmable between different impedance states by a reduction-oxidation reaction within at least one memory layer formed between two electrodes; wherein the tunneling access device and programmable impedance element are vertically stacked over one another.

Memory cells with vertically integrated tunnel access device and programmable impedance element

In one embodiment, a capacitive circuit can include: (i) a resistive storage element having a solid electrolyte, a first electrode coupled to a first side of the solid electrolyte, and a second electrode coupled to a second side of the solid electrolyte; (ii) the resistive storage element being configured to be programmed to a low resistance state by application of a program voltage in a forward bias direction to form a conductive path between the first and second electrodes, and being configured to be erased to a high resistance state by application of an erase voltage in a reverse bias direction to substantially dissolve the conductive path; and (iii) a first capacitor having the first electrode coupled to a first side of a first oxide layer, and a third electrode coupled to a second side of the first oxide layer.

Capacitor arrangements using a resistive switching memory cell structure

Structures and methods of operating a resistive switching memory device are disclosed herein. In one embodiment, a resistive switching memory device can include: (i) a plurality of resistive memory cells, where each of the resistive switching memory cells is configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and to be erased to a high resistance state by application of a second voltage in a reverse bias direction; and (ii) a sensing circuit coupled to at least one of the plurality of resistive memory cells, where the sensing circuit is configured to read a data state of the at least one resistive memory cell by application of a third voltage in the forward bias direction or the bias reverse direction.

Sensing data in resistive switching memory devices

Structures and operations of a resistive switching memory device are described herein. In one embodiment, a resistive switching memory device can include: a plurality of resistive memory cells, each configured to be programmed to a low resistance state by application of a first voltage in a forward bias direction, and erased to a high resistance state by application of a second voltage in a reverse bias direction; a plurality of common plates, each being connected to a subset of the resistive memory cells; a command detector configured to detect a write command to be executed as a first and second write operations; and a write controller configured to perform the first write operation on each resistive memory cell in a selected subset, and to perform the second write operation on at least one of the resistive memory cells in the selected subset based on the detected write command.

Growing community of inventors

Dublin, CA, United States of America

John Dinh