St-Ericsson Sa

Koninklijke Philips Corporation N.v.

Nxp B.v.

John Dielissen

Edwin Rijpkema

An LDPC decoder iteratively decodes an LDPC code represented by a parity check matrix H consisting of a plurality of circulants based on a Log-Likelihood Ratio Belief-Propagation algorithm. First computation means () compute for a next iteration symbol messages &#x3bb;from a representation of a corresponding symbol value stored in a first memoryand from check node messages &#x39b;from a previous iteration. A shuffler () changes a sequence of the symbol message received from the first computation means () in dependence on a position of the non-zero elements in a corresponding sub-matrix. Second computation means (DP-O, DP-I, DP-D-I) compute the check node messages in dependence on symbol messages received from the barrel shifter and store a representation of the computed check node message in a second memory (). Third computation means () update the representation of the symbol values in the first memory in dependence on output of the first and second computing means. The principle of 'staggered' or 'shuffled' LDPC decoding is used. One embodiment is designed for multi-diagonal circulants.

Shuffled LDPC decoding

An electronic device is provided which comprises a barrel shifter unit (BS) for performing a rotation of an input. The barrel shifter unit comprises a first and second barrel shifter (BS, BS). The electronic device furthermore comprises a selection unit for selecting a first set of elements (a) for the second barrel shifter (BS) and a second set of elements for the first barrel shifter (BS). The electronic device furthermore comprises a plurality of second multiplexers (MM) for receiving the input of the second barrel shifter as first input and the output of the first barrel shifter as second input.

Electronic device, barrel shifter unit and method of barrel shifting

An integrated circuit includes functional blocks and a data communication network having network stations interconnected via communication channels for communicating data packages between the functional blocks. Each data package includes N data elements having a data element with routing information for the network stations, N being an integer of at least two. The network stations include data routers and network interfaces, where each of the data routers is coupled to a functional block via a network interface. The data communication network includes first and second network stations interconnected through a first communication channel. The network includes M*N data storage elements, M being a positive integer, for introducing a delay of M*N cycles on the first communication channel.

Integrated circuit with data communication network and IC design method

An integrated circuit comprises a plurality of data processing circuits () and a communication network () coupled between the data processing circuits (). The communication network () comprises connections () and router circuits () coupled between the connections (). Memory is provided to store definitions for respective data streams, of respective paths along the connections (), for controlling the router circuits () to transmit each data item from each respective data stream along the respective path programmed for that respective data stream. Initially initial paths for a set of original data streams are defined and started. Subsequently an additional data stream can be added. If so a new path is selected in combination with future paths for the original data streams. The combination of the new paths and the future paths is taken from selectable combinations that include at least one combination wherein an initial path for at least one of the original data streams has been rerouted with respect to the initial path. The initial path for the at least one of the original data streams is reprogrammed if the path for that original data stream is rerouted in the selected combination, without interrupting transmission of data items of data streams other than the at least one of the original data streams. Subsequently transmission of data items is started along the new path.

Integrated circuit with internal communication network

An electronic device is provided which comprises an interconnect means (N) for coupling a plurality of processing modules (IP-IP) to enable a communication between the processing modules (IP-IP). The electronic device further comprises a plurality of network interfaces (NI) for coupling the interconnect means (N) to one of the processing modules (IP-IP). Furthermore, at least one time slot allocating unit (SA) is provided for allocating time slots to channels of the interconnect means (N). The time slot allocating unit (SA) comprises a plurality of slot tables (T-T) with a plurality of entries. Each entry corresponds to a fraction of the available bandwidth of the interconnect means (N). A first slot table of the plurality of slot tables (T-T) comprises at least one first entry of the plurality of entries which relates to a second slot table of the plurality of slot tables (T-T).

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Weert, Netherlands

John Dielissen