Intel Corporation

John Decker

Robert M Nickerson

Nisha Ananthakrishnan

Amram Eitan

Purushotham Kaushik Muthur Srinath

Shripad Gokhale

Elizabeth Nofen

Hsin-Yu Li

Yang Guo

Nick Ross

Vipul V Mehta

Yiqun Bai

Ziyin Lin

Yan Li

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and PoP adhesive keep out zone

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and pop adhesive keep out zone

Microelectronics package comprising a package-on-package (POP) architecture with inkjet barrier material for controlling bondline thickness and POP adhesive keep out zone

An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a mold material layer abutting electronic substrate and substantially surrounding the at least one integrated circuit, and at least one structure within the mold material layer, wherein the at least one structure comprises a material having a modulus of greater than about 20 gigapascals and a thermal conductivity of greater than about 10 watts per meter-Kelvin.

High thermal conductivity, high modulus structure within a mold material layer of an integrated circuit package

Embodiments disclosed herein include composite dies and methods of forming such composite dies. In an embodiment, a composite die comprises a base substrate, a first die over the base substrate, and a second die over the base substrate and adjacent to the first die. In an embodiment an underfill layer is between the first die and the base substrate, between the second die and the base substrate, and between the first die and the second die. In an embodiment, a trench into the underfill layer is between the first die and the second die. In an embodiment the composite die further comprises, a mold layer over the first die and the second die, wherein the mold layer fills the trench.

Trenches in wafer level packages for improvements in warpage reliability and thermals

Growing community of inventors

Tempe, AZ, United States of America

John Decker