Motorola Corporation

Semiconductor Components Industries, LLC

Other

John David Moran

Blanca Estela Kruse

Ali Salih

Peyman Hadizad

Mark Duskin

John R Bender

Linghui Chen

Amilcar B Gamez Sanchez

Jose Rogelio Moreno

A flip chip structure includes glass stand-offs formed overlying a substrate surface. A conductive layer is formed overlying the glass stand-offs and configured for attaching to a next level of assembly. In one embodiment, photo glass processing is used to form the glass stand-offs.

Flip chip structure and method of manufacture

A Schottky diode capable of sustaining a voltage of greater than about 250 volts and a method for its manufacture. An epitaxial layer of N-type conductivity is disposed on a semiconductor substrate of N-type conductivity. A guard ring of P-type conductivity extends into the epitaxial layer from its surface. A stacked structure is formed on a portion of the guard ring and a portion of the epitaxial layer. The stacked structure includes a layer of semi-insulating semiconductor material disposed on a layer of dielectric material. A first metal layer is formed on the portion of the epitaxial layer adjacent a first side of the stacked structure and on a first portion of the stacked structure. A second metal layer is formed on the portion of the epitaxial layer adjacent a second side of the stacked structure and on a second portion of the stacked structure.

Schottky diode and method of manufacture

In one embodiment, a diode is formed with anodes on two surfaces of a semiconductor substrate.

Semiconductor diode and method therefor

A semiconductor structure (10) uses a clamp (16) disposed at an edge (27) of a dielectric structure (14) in a semiconductor device. The clamp substantially reduces the separation or peeling of the dielectric structure or layer away from the underlying semiconductor material (20,24). The clamp also provides the benefit of protecting the interface between the dielectric layer and the underlying semiconductor material from chemical or moisture attack, either during later processing or after final manufacture. Such chemical or moisture attack and internal film stress are factors leading to separation of the dielectric film from the underlying semiconductor material. The clamp is useful, for example, in preventing separation of silicon nitride or oxide passivation from gallium arsenide substrates in power rectifier diodes.

Clamp disposed at edge of a dielectric structure in a semiconductor

A method of manufacturing a semiconductor component includes sputtering a first metal layer (16) over a substrate (11), sputtering a second metal layer (17) over the first metal layer (16), selectively etching the second metal layer (17) versus the first metal layer (16), selectively etching the first metal layer (16) versus the second metal layer (17), and thereafter, selectively re-etching the second metal layer (17) versus the first metal layer (16).

Method of etching adjacent layers

Semiconductor device structures having very smooth surfaces and very high doping levels of opposite types present on the same wafer may be plated in the same electroless plating bath without differentiation between the N and P regions or rough and smooth surface regions. This is achieved by a pre-treatment involving coating the wafer surface with a metal salt (e.g., NiCl in glycol and water) and reducing the metal salt in an oxygen free atmosphere (e.g., hydrogen) at a temperature (e.g., &gt;300.degree. C. for Si) sufficient to promote formation of an intermetallic between the reduced metal and the semiconductor substrate. This provides very uniform and effective nucleation sites for the subsequent electroless plating process irrespective of the smoothness, doping type and doping density of the semiconductor surface.

Method for forming semiconductor contacts by electroless plating

Rectifiers of excellent characteristics may be more economically fabricated by a process in which a cavity is first etched in a non-epitaxial semiconductor wafer to a depth in the range of typically 15-25 percent of the initial wafer thickness. Simultaneous diffusion of N and P type dopants is used to provide (for an N type substrate) a P+ region in the bottom of the cavity and surrounding surface, and an N+ region on the opposite face of the wafer. A mask is then provided in the cavity bottom and the surrounding wafer regions etched to remove the P+ dopant outside the cavity thereby re-exposing the surrounding region of the original N type substrate. The P+ region may be level with or protrude slightly from the substrate surface. The junction formed between the P+ region in the cavity bottom and the N type substrate has a gradual contour where it intersects the surface thereby providing a more favorable field distribution. Passivation and metallization are provided in the conventional manner. The resulting devices may be fabricated in very thin wafers without significant mechanical breakage loss.

Method for manufacturing semiconductor rectifier

A thermal timing device formed by a meat thermometer provided with a removable heat insulating shroud or jacket. The meat thermometer may be used in the usual fashion without the jacket to indicate the extent to which meat is roasted. With the jacket in place on the thermometer, the timing device may then be used for controlling other cooking processes such as broiling, baking, deep fat frying, and boiling.

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Mesa, AZ, United States of America

John David Moran