International Business Machines Corporation

Globalfoundries Inc.

John David McCalpin

Francis Patrick O'Connell

Ravi Kumar Arimilli

William John Starke

Balaram Sinharoy

Kenneth Lee Wright

Steven Wayne White

Yaoqing Gao

Robert J Blainey

Roch Georges Archambault

Patrick N Conway

Pascal Vezolle

Dereck Edward Williams

In one embodiment, a system comprises a first processor, a main memory system, and a cache hierarchy coupled between the first processor and the main memory system. The cache hierarchy comprises at least a first cache. The first processor is configured to execute a first instruction, including forming an address responsive to one or more operands of the first instruction. The system is configured to push a first cache block that is hit by the first address in the first cache to a target location within the cache hierarchy or the main memory system, wherein the target location is unspecified in a definition of the first instruction within an instruction set architecture implemented by the first processor, and wherein the target location is implementation-dependent.

Push for sharing instruction

A method and system of modifying instructions forming a loop is provided. A method of modifying instructions forming a loop includes modifying instructions forming a loop including: determining static and dynamic characteristics for the instructions; selecting a modification factor for the instructions based on a number of separate equivalent sections forming a cache in a processor which is processing the instructions; and modifying the instructions to interleave the instructions in the loop according to the modification factor and the static and dynamic characteristics when the instructions satisfy a modification criteria based on the static and dynamic characteristics.

Method and system for code modification based on cache structure

A microprocessor and a related compiler support a local cache block flush instruction in which an execution unit of a processor determines an effective address. The processor forces all pending references to a cache block corresponding to the determined effective address to commit to the cache subsystem. If the referenced cache line is modified in the local cache (the cache subsystem corresponding to the processor executing the instruction), it is then written back to main memory. If the referenced block is valid in the local cache it is invalidated, but only in the local cache. If the referenced block is not valid in the local cache, there is no invalidation. Remote processors receiving a local cache block flush instruction from another processor via the system ignore the instruction.

Localized cache block flush instruction

A method and apparatus for managing cache lines in a data processing system. A special purpose register is employed in which this register may be manipulated by user code and operating system code to set preferences, such as a level 2 cache management policy preference for an application thread. These preferences may be dynamically set and an arbitration mechanism is employed to best satisfy preferences of multiple threads with a single aggregate preference. Members are represented using a least recently used tree. The least recent used tree has a set of nodes forming a path to member cache lines in a hierarchical structure. A state of a selected node is selectively biased within the set of nodes in the least recently used tree. At least one node on a level below the selected node is eliminated from being selected in managing the cache lines. In this manner, members can be biased against or for selection as victims when replacing cache lines in a cache memory.

Programming means for dynamic specifications of cache management preferences

Growing community of inventors

Round Rock, TX, United States of America

John David McCalpin