Marvell International Technology Ltd

Marvell International Limited

John David Marshall

Douglas G Keithley

Richard David Taylor

Mark David Montierth

Gary D Zimmerman

Melvin D Bodily

William Randolph Schmidt

Roy Gideon Moss

Gordon R Clark

Gregory R Smith

A system and method for processing digital images that efficiently buffers pixel data relating to digital images is disclosed. Pixel values are read from an image storage memory and temporarily stored in a buffer memory according to a non-raster pattern. The processing of pixels also occurs according to a more efficient non-raster patter.

Non raster row pixel processing

A pulse width modulation technique is disclosed for use in an image forming device such as a laser printer or a photocopier. The technique implements a pacer to synthesize the frequency of a serializer circuit by stretching (or shrinking) pixel pulse train data. The pacer stretches the pixel pulse train data in accord with increment data that is based upon information about the image forming device, such as the number of bits in the pixel pulse train data, the number of bits in print engine pulse train, the target print engine frequency, and the serializer frequency. The technique can be implemented with digital circuits that provide digital test data.

Pulse width modulator for a printing device

A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implemented using a few terminals of the ASIC.

Built-in-self-test using embedded memory and processor in an application specific intergrated circuit

A direct memory access controller is set forth. The direct memory access controller includes first and second registers storing various values that are used to set the parameters of DMA transfers that take place during a single data transaction. The first register stores a start address location value used to define a start address at which direct memory access transfers for the transaction are to begin. The second register stores a value used to end data transfers of the data transaction. The DMA controller also includes transfer control circuitry for executing the data transaction. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the values stored in the first and second registers.

Direct memory access controller with multiple transaction functionality

A system and method for processing digital images that efficiently buffers pixel data relating to digital images is disclosed. Pixel values are read from an image storage memory and temporarily stored in a buffer memory according to a non-raster pattern. The processing of pixels also occurs according to a more efficient non-raster pattern.

A test method for an ASIC uses an embedded processor in the ASIC to execute test routines from an embedded memory or an external memory. During ASIC production, the test routines can comprehensively test of the blocks of the ASIC without a complicated test pattern from test equipment. The test routines can also perform power-up tests in systems or end products containing the ASIC. Test selection, activation, and result output can be implement using a few terminals of the ASIC.

Built-in-self-test using embedded memory and processor in an application specific integrated circuit

A method and apparatus for handshaking using a 2-wire protocol is described. An electronic component may be divided into blocks, with the blocks performing one or more functions. The blocks may be in series with one another to form a pipeline. The blocks may use interface circuitry to transfer information upstream from or downstream to another block. The interface circuitry uses the 2-wire handshaking for the transfer including a transmit readiness wire configured to carry a signal indicative of readiness of the upstream circuit to output data and a receive readiness wire configured to carry a signal indicative of readiness of the downstream circuit to receive the data.

Common block interface for data and protocol with handshake

Common block interface for data and control with handshake protocol

Built-in self-test using embedded memory and processor in an application specific integrated circuit

A laser print apparatus includes a memory for storing a multi-bit image including a plurality of pixels. Each pixel is represented by an N-bit value, wherein N is greater than one. A modulation code generator analyzes three adjacent pixels. The three adjacent pixels include a left pixel, a center pixel, and a right pixel. The modulation code generator is configured to generate a pulse width value based on the value of the center pixel, and a justification value based on the values of the left pixel and the right pixel. A laser print engine forms an output pixel on media based on the pulse width value and the justification value.

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Boise, ID, United States of America

John David Marshall