International Business Machines Corporation

John David Jabusch

Howard Thomas Olnowich

Robert Francis Lusch

Gordon Taylor Davis

Brett Olsson

Sumedh Wasudeo Sathaye

Eric Francis Robinson

Richard William Doing

Jeffrey Richard Summers

M V V Anil Krishna

James William Feeney

Michael Hans Fisher

Michael Anthony Maniguet

Joel M Gould

Jehoshua Bruck

Arthur Robert Williams

Michael W Dotson

Agnes Yee Ngai

George William Wilhelm, Jr

Barbara A Hall

Ronny Morad

Robert Reist Richardson

Shady Copty

Kevin C Huang

Alex Goryachev

Shimon Ben-Yehuda

Linda Anne Kovacs

Timothy G Plzak

A system-level testcase may be generated by performing system-level generation tasks by a system-level generator to produce an abstract testcase. Based upon the abstract testcase, one or more unit-level generators may generate the testcase. The testcase may be utilized in simulation of operation of a system-under-test (SUT). The testcase may be utilized for verification of the SUT. The SUT may comprise a plurality of units. The unit-level generator may be associated with units of the SUT and perform generation tasks associated with pertinent units.

System-level testcase generation

A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.

Structure for supporting simultaneous storage of trace and standard cache lines

A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.

Apparatus and method for using branch prediction heuristics for determination of trace formation readiness

A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. A mechanism is described for indexing into the cache, and selecting the desired line. Control is exercised over which lines are contained within the cache. Provision is made for selection between a trace line and a conventional line when both match during a tag compare step.

Apparatus and method for supporting simultaneous storage of trace and standard cache lines

A single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines. Power is conserved by guiding access to lines stored in the cache and lowering cache clock speed relative to the central processor clock speed.

Apparatus and method for saving power in a trace cache

An apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. The apparatus is relatively easy to implement and inexpensive to build. The communication media is switch-based and is fully parallel, supporting nodes interconnected by the switching network.

Apparatus for coupling a bus-based architecture to a switch network

The multi-stage interconnection network of the present invention includes the use of switches in the first stage that have parallel path seeking capabilities. With these switches, a directed flash-flood can be instigated from any one node wherein multiple paths through the network to a designated destination node are tried in parallel in an attempt to find a connection path therebetween. The switches in the first and second stages are interconnected such that each switch in the first stage is connected with every possible priority level to the switches of the second stage. The parallel path seeking switches and network are further configured to test for rejection of the flash-flood by monitoring all connections in combination.

Method of simultaneously attempting parallel path connections in a

A method and hardware apparatus provide a fault tolerant and flexible multi-stage network addressing scheme for transmitting a message with a header containing control bits for selecting from various destination checking functions to be performed. Upon arrival of the message at a node, destination checking is performed or not in response to the massage's header. If destination checking is not performed, or if destination checking is performed and indicates that the node is the desired destination for the message, the message is accepted. If destination checking is performed and indicates that the node is not the desired destination for the message, the message is rejected. Destination checking is disabled during address assignment, broadcasting and multi-casting, and replaced with one's complement-based verification of the sending node.

Selectable checking of message destinations in a switched parallel

A multi-stage interconnection network includes the use of switches in the first stage that have parallel path seeking capabilities. With these switches, a directed flash-flood can be instigated from any one node wherein multiple paths through the network to a designated destination node are tried in parallel in an attempt to find a connection path therebetween. The switches in the first and second stages are interconnected such that each switch in the first stage is connected with every possible priority level to the switches of the second stage. The parallel path seeking switches and network are further configured to test for rejection of the flash-flood by monitoring all connections in combination.

Flash-flooding multi-stage interconnection network with parallel path

A conversion apparatus that converts and adapts standard processor bus protocol and architecture, such as the MicroChannel (IBM Trademark) bus, to more progressive switch interconnection protocol and architecture. Existing bus-based architecture is extended to perform parallel and clustering functions by enabling the interconnection of thousands of processors. A conversion apparatus controls the transfer of data messages from one nodal element across a switch network to another nodal element by using direct memory access capabilities controlled by intelligent bus masters. This approach does not require interactive support from the processor at either nodal element during the message transmission, and frees up both processors to perform other tasks. The communication media is switch-based and is fully parallel, supporting n transmissions simultaneously, where n is the number of nodes interconnected by the switching network.

Apparatus for adapting message protocols for a switch network and a bus

An electronic switching and data transmission system for interconnecting a plurality of buses. A switching network interconnects several multi-drop buses using adapters to connect the buses to the switching network. The adapters implements hardware functions to appear to software as if all devices on the several buses were attached to a single large bus. The system permits higher speed transfer modes by eliminating multi-drop bus limitations.

Switch network extension of bus architecture

A checkpoint retry system for recovery from an error condition in a multiprocessor type central processing unit which may have a store-in or a store-through cache system. At detection of a checkpoint instruction, the system initiates action to save the content of the program status word, the floating point registers, the access registers and the general purpose registers until the store operations are completed for the checkpointed sequence. For processors which have a store-in cache, modified cache data is saved in a store buffer until the checkpointed instructions are completed and then written to a cache which is accessible to other processors in the system. For processors which utilize store-through cache, the modified data for the checkpointed instructions is also stored in the store buffer prior to storage in the system memory.

Central processing unit checkpoint retry for store-in and store-through

A broadcast/switching apparatus makes input port to output port connections on a requested basis quickly and dynamically in a standard mode from any one of the input ports to any one of the output ports, in a multi-cast mode from any one of the input ports to a fixed number of subsets of multiple output ports simultaneously, or in a broadcast mode from any one of the input ports to all output ports simultaneously, using a new asynchronous approach to resolve either broadcast or multi-cast contention among input ports. The normal mode of the broadcast/switch apparatus requires absolutely no synchronization among any of the input and output ports which interface to the apparatus. The broadcast/switch apparatus also incorporates a new accept protocol that enables a positive feedback indication to be returned to the sender of a multi-cast or broadcast operation to inform it that the multi-cast or broadcast transmission was correctly received by all elements involved in the multi-cast or broadcast. The broadcast/switch is completely void of centrally controlled clocking and data buffering. Data which traverses the switch encounters only three gate delays--on-chip receiver, mux, and off-chip driver. Contention is detected and resolved on chip. Each broadcast/switch port interface requires several parallel data lines plus four control lines.

Broadcast/switching apparatus for executing broadcast/multi-cast

Disclosed is multi-media switching apparatus for performing digital, analog, and/or optical communications amongst multiple nodes over switching networks. The key aspect of the present invention is the full parallel aspect of the switching apparatus which supports n simultaneously, low-latency connections, where n is the number of functional elements interconnected by the switching network. Any of the n simultaneous transmissions can be digital, analog, or optical in any proportion. In addition, the present invention can also serve as a high-speed distributed controller for the purpose of of selecting analog or optical switches for information transfer between elements of the system.

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Cary, NC, United States of America

John David Jabusch