Micron Technology Incorporated

Intel Corporation

Other

Lodestar Licensing Group LLC

John David Hopkins

Jordan D Greenlee

Alyssa N Scarbrough

Nancy M Lomeli

Gordon A Haller

Hongbin Zhu

Fatma Arzum Simsek-Ege

Rita J Klein

Justin B Dorhout

Roger W Lindsay

Damir Fazil

Collin Howder

Kunal Shrotri

David A Daycock

Zhenyu Lu

Jie Sun

Yushi Hu

Purnima Narayanan

Darwin A Clampitt

Lifang Xu

Luan C Tran

Akira Goda

Everett Allen McTeer

Shuangqiang Luo

Christopher J Larsen

Vinayak Shamanna

Shyam Surthi

Richard J Hill

Anish A Khandekar

Fei Wang

Daniel Billingsley

Charles H Dennison

Yongjun Jeff Hu

Indra V Chary

Matthew J King

Darwin Franseda Fan

Tom Jibu John

Srikant Jayanti

Jiewei Chen

Chet E Carter

M Jared Barclay

John Mark Meldrim

Changhan Kim

Kunal R Parekh

Krishna Kumar Parat

Martin Ceredig Roberts

Swapnil Lengade

Aaron R Wilson

Qian Tao

Matthew Park

Randy J Koval

Yiping Wang

Jivaan Kishore Jhothiraman

Ryan L Meyer

Ian C Laboriante

Justin D Shepherdson

Merri Lyn Carlson

Rohit Kothari

Meng-Wei Kuo

Kar Wui Thong

Paolo Tessariol

Xiao Li

Adam L Olson

Brett D Lowe

Harsh Narendrakumar Jain

Andrew Li

Dimitrios Pavlopoulos

Brian J Cleereman

James Mathew

Aurelio Giancarlo Mauri

Prasanna Srinivasan

Jeslin J Wu

David H Wells

Ronald Allen Weimer

Anilkumar Chandolu

Christopher W Petz

Sanjeev Sapra

Alex J Schrinsky

Peng Xu

Shawn D Lyonsmith

Luca Fumagalli

Haoyu Li

Marko Milojevic

Chris Larsen

Jun Fang

John A Smythe

George Matamis

Allen McTeer

Adam William Saxler

Zahra Hosseinimakarem

Silvia Borsari

Yi Hu

David Ross Economy

Erik R Byers

Xiaosong Zhang

Jie Li

Grady S Waldo

Francois H Fabreguette

Ramey M Abdelrahaman

Shen Hu

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. A lower of the first tiers comprises sacrificial material. A horizontally-elongated slot is formed through the first and second tiers to the sacrificial material in individual of the memory-block regions to form laterally-spaced sub-block regions in the individual memory-block regions. The sacrificial material is isotropically etched from the lower first tier through the horizontally-elongated slots. After the isotropic etching, conducting material is formed in the horizontally-elongated slots and in the lower first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. After forming the conducting material, horizontally-elongated trenches are formed through the first tiers and the second tiers and that are individually laterally between immediately-adjacent of the memory-block regions. Other embodiments, including structure independent of method, are disclosed.

Method used in forming a memory array comprising strings of memory cells comprising forming trenches between memory-block regions after forming trenches to form laterally-spaced sub-block regions in the memory-block regions

A microelectronic device includes a source stack, a source contact vertically adjacent to the source stack, a semiconductor material vertically adjacent to the source contact, tiers of alternating conductive materials and dielectric materials vertically adjacent to the semiconductor dielectric material, a dielectric structure within a slot structure and extending through the tiers of the microelectronic device to the source contact of the microelectronic device, oxide cap structures laterally between the semiconductor material and the dielectric structure, and pillars extending through the tiers, the semiconductor material, and the source contact and into the source stack. Related electronic systems and methods are also disclosed.

Microelectronic devices including cap structures, and related electronic systems and methods

Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and said other region, and separates a first memory-block-region from a second memory-block-region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. Rings laterally surround lower regions of the conductive posts. The rings are between the conductive posts and the doped-semiconductor-material. The rings include laminates of two or more materials, with at least one of said two or more materials being insulative. Some embodiments include methods for forming integrated assemblies.

Integrated assemblies and methods of forming integrated assemblies

A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers directly above the conductor tier. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The channel material of individual of the channel-material strings is directly electrically coupled to the conductor material of the conductor tier. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises insulating material. The conductor material in the conductor tier comprises a pair of side interfaces that individually extend downwardly from a top of the conductor tier on one of opposing sides of the intervening material and individually extend longitudinally-along the immediately-laterally-adjacent memory blocks. The side interfaces have the conductor material laterally-over opposing sides thereof. Other embodiments, including method, are disclosed.

Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a first vertical stack comprising vertically-alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. A second vertical stack is aside the first vertical stack. The second vertical stack comprises insulative tiers collectively comprising at least two different compositions relative individual of the insulative tiers. Individual of the at least two different compositions comprise silicon nitride. One of the individual different compositions comprise carbon-doped silicon nitride having at least 0.5 atomic percent more carbon than atomic percent of carbon, if any, in the silicon nitride of another of the individual different compositions. Other embodiments, including method, are disclosed.

Methods used in forming memory arrays having strings of memory cells

Microelectronic devices include a stack structure of vertically alternating insulative and conductive structures arranged in tiers. The insulative structures of a lower portion of the stack structure are thicker than the insulative structures of an upper portion. The conductive structures of the lower portion are as thick, or thicker, than the conductive structures of the upper portion. At least one feature may taper in width and extend vertically through the stack structure. The thicker insulative structures of the lower portion extend a greater lateral distance from the at least one feature than the lateral distance, from the at least one feature, extended by the thinner insulative structures of the upper portion. During methods of forming such devices, sacrificial structures are removed from an initial stack of alternating insulative and sacrificial structures, leaving gaps between neighboring insulative structures. Conductive structures are then formed in the gaps. Systems are also disclosed.

Microelectronic devices with tier stacks with varied tier thicknesses, and related methods and systems

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed and individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor material between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material that is laterally-between the horizontally-elongated lines. After the horizontally-elongated lines are formed, conductive material of a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier, Other embodiments, including structure independent of method, are disclosed.

Some embodiments include a method of forming a conductive structure. A metal-containing conductive material is formed over a supporting substrate. A surface of the metal-containing conductive material is exposed to at least one radical form of hydrogen and to at least one oxidant. The exposure alters at least a portion of the metal-containing conductive material to thereby form at least a portion of the conductive structure. Some embodiments include a conductive structure which has a metal-containing conductive material with a first region adjacent to a second region. The first region has a greater concentration of one or both of fluorine and boron relative to the second region.

Metal-containing structures, and methods of treating metal-containing material to increase grain size and/or reduce contaminant concentration

A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor tier between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material and comprise metal material. After the horizontally-elongated lines are formed, conductive material is formed in a lower of the first tiers and that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, the tiers including respective memory cells and control gates for the memory cells; a first pillar extending through the tiers and separated from the control gates, the first pillar including a first dielectric liner portion and a first core portion adjacent the first dielectric liner portion, the first dielectric liner portion and the first core portion extending along a length of the first pillar; and a second pillar extending through the tiers and separated from the control gates, the second pillar including a second dielectric liner portion and a second core portion adjacent the second dielectric liner portion, the second dielectric portion and the second core portion extending along a length of the second pillar, wherein the first core portion and the second core portion have different materials.

Memory device including support structures and contact structures having different materials

Methods, systems, and devices for self-aligned etching techniques for memory formation are described. A memory device may include a stack of alternating materials and a pillar extending through the stack of alternating materials, where the stack of alternating materials and the pillar may form a set of multiple memory cells. A polysilicon material may be formed above the pillar, where the polysilicon material may be associated with a selector device for the memory cells. A masking material may be formed above the polysilicon material and the stack of alternating materials, where the masking material may be aligned with the polysilicon material and may have a width that is greater than a width of the polysilicon material and the pillar. The masking material may prevent the polysilicon material, the pillar, and a portion of the stack of alternating materials beneath the masking material from being removed during an etching operation.

Self-aligned memory architecture comprising a memory array associated with pillars and polysilicon material

Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies which include stacked memory decks, and methods of forming integrated assemblies

Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks that individually comprise a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises alternating first insulating tiers and second insulating tiers. The lower portion comprises a lowest insulator tier directly above conductor material of a conductor tier. The lowest insulator tier comprises solid carbon and nitrogen-containing material. An immediately-adjacent tier is directly above the solid carbon and nitrogen-containing material of the lowest insulator tier. The immediately-adjacent tier comprises material that is of different composition from that of the lowest insulator tier. Other embodiments, including methods, are disclosed.

Integrated circuitry and method used in forming a memory array comprising strings of memory cells

Methods, systems, and devices for a barrier structure for preventing removal of, such as etching to, control circuitry are described. A memory device may include control circuitry over a substrate and for accessing a memory array and contact regions configured to couple with the control circuitry. The memory device may include barrier regions between respective contact regions that includes a barrier material. The memory device may include a stack of layers over the barrier region and the contact regions that is associated with the memory array, and the barrier material may prevent a removal (e.g., an etch) through the stack of layers and at least partially between contact regions from extending to the control circuitry.

Barrier structure for preventing etching to control circuitry

A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lower-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-second-tiers or a lower of the upper-second-tiers comprises non-stoichiometric silicon dioxide that has a silicon-to-oxygen atomic ratio greater than 0.5. A higher of the upper-second-tiers that is above said lower upper-second-tier comprises silicon dioxide that has a silicon-to-oxygen atomic ratio less than or equal to 0.5. Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-second-tier or said lower upper-second-tier. After the stop, the sacrificial material is removed from the lower channel openings and channel-material strings are formed in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.

Integrated circuitry comprising a memory array comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

Growing community of inventors

Meridian, ID, United States of America

John David Hopkins