Tandem Computers Incorporated

John David Allison

Robert W Horst

Kenneth C Debacker

Douglas E Jewett

Richard W Cutts, Jr

Nikhil A Mehta

Charles E Peet, Jr

Richard A Southworth

Peter C Norwood

A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.

Interrupts between asynchronously operating CPUs in fault tolerant

Refresh control for dynamic memory in multiple processor system

Fault-tolerant computer with three independently clocked processors

A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. Each CPU has a local memory, separate from the memory modules, and this local memory is of the dynamic type so it must be periodically refreshed. The refresh cycles are interposed at the same point in the instruction stream for each of the three CPUs by counting instruction execution cycles separately in each CPU, and interrupting to do a refresh cycle when a given count is reached. Stall cycles are also counted, and when long periods of stalls occur then more than one refresh cycle is interposed to catch up to the needed refresh schedule.

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John David Allison