Altasens, Inc.

Alcatel

Teledyne Scientific and Imaging, LLC

Alcatel Internetworking, Inc.

Xylan Corporation

John Daniel Wallner

Michael Jon Nishimura

Michael K Wilson

Laurent Blanquart

Christopher Leo Hoogenboom

Chris L Hoogenboom

John Richardson

John W Bailey

Todd Khacherian

Qianjiang Mao

Roberto Marchesini

Joey Shah

Giuseppe Rossi

Manjunath Subray Bhat

Ying Huang

Michael Gorder

Jeff Miller

Steve Senum

Todd L Khacherian

Qianjiang (Bob) Mao

Mike Wilson

Joe Golio

Bob Kowalski

An SEU protection circuit comprises first and second storage means for receiving primary and redundant versions, respectively, of an n-bit wide data value that is to be corrected in case of an SEU occurrence; the correction circuit requires that the data value be a 1-hot encoded value. A parity engine performs a parity operation on the n bits of the primary data value. A multiplexer receives the primary and redundant data values and the parity engine output at respective inputs, and is arranged to pass the primary data value to an output when the parity engine output indicates 'odd' parity, and to pass the redundant data value to the output when the parity engine output indicates 'even' parity. The primary and redundant data values are suitably state variables, and the parity engine is preferably an n-bit wide XOR or XNOR gate.

Single event upset protection circuit and method

Systems and methods are provided to implement a state map to control operations of a complementary metal-oxide-semiconductor (CMOS) sensor. The state map can be a table comprising one or more locations. Each of the locations can comprise a destination state to define the operations of the sensor and an exit criterion to advance to a next location in the state map. For example, an operation sequence can be implemented using the state map to instruct the CMOS sensor to perform a specific set of operations. Further, a data value to represent the destination state and/or a variable input can be stored in a writable address of a register. Thus, a simplified architecture can be provided to implement CMOS sensor operation states, for instance, to improve interactions between real time and non-real time signals and to increase functionality of the CMOS sensor.

Sensor state map for managing operational states of an image sensor

Providing for pausing data readout from an optical sensor array is described herein. By way of example, an interruption period can be introduced into a readout cycle of the optical sensor array to suspend readout of data. During the interruption period, other operations related to the optical sensor array can be performed, including operations that are typically detrimental to image quality. Moreover, these operations can be performed while mitigating or avoiding negative impact on the image quality. Thus, greater flexibility is provided for global shutter operations, for instance, potentially improving frame rates and fine control of image exposure, while preserving image quality.

Pausing digital readout of an optical sensor array

A method for correcting column Fixed Pattern Noise (FPN) in an image sensor offers a compromise between speed and precision for calculating column FPN offsets. The present correction technique is digital, and is applied after the pixel signal voltages have been digitized by an ADC. A first Optical Black (OB) pixel is sampled and compared to a target level. An offset is stored, and an appropriate push-size is determined. Additional OB pixels are sampled and the offset is applied. The push-size is increased or decreased depending upon whether the pixel signal with the applied offset is above or below a target value. This new offset value is written to memory, and the push-size is reduced, and the process is repeated until the last OB pixel has been processed. The resulting offset is applied to the signal pixels in a column. The primary advantage of this approach is that within a single frame, a good estimate of the column offset is made which is not as affected by outlier pixels (such as 'hot' or 'flashing' pixels).

Method for fixed pattern noise (FPN) correction

Programmable data readout for optical image sensors is disclosed herein. By way of example, vertical skipping and vertical mixing functionality is provided that is responsive to commands, enabling dynamic selectivity and processing of optical sensor data. A data output control system can be incorporated with or coupled to data readout circuitry of an optical sensor. The output control system comprises a vertical skipping engine that can dynamically select a subset of data for output in response to one or more skipping commands, and a vertical mixing engine that can act upon subsets of data in accordance with processing functions called by respective mixing commands. The disclosure provides simplification of selective data readout and processing for image sensors, potentially reducing design, testing, and maintenance overhead, as well as cost and number of integrated circuit components.

Programmable data readout for an optical sensor

The claimed subject matter provides systems and/or methods that facilitate controlling timing dependencies in a mixed signal circuit. Timing performance associated with a horizontal scanner and an analog to digital converter (ADC) can be monitored. Moreover, data related to the monitored timing performance can be leveraged to modify timing parameter(s) of clocks that coordinate operations of the horizontal scanner and the ADC (e.g., and/or digital component(s) included in the mixed signal circuit). For example, the clocks associated with the horizontal scanner and the ADC can be independently tuned to optimize mixed signal circuit performance.

Controlling timing dependencies in a mixed signal system-on-a-chip (SOC)

A black clamp stabilization circuit for an image sensor utilizes a mixed-signal SoC block comprising sub-blocks to dynamically and precisely adjust the black level based on comparison to a reference black level. The black level adjustments include a first level regulation using digital control of an analog signal in a feedback loop that includes a programmable gain amplifier and high-resolution A/D converter. By applying the black clamping in the analog domain, dynamic range is extended. Additional black level regulation is subsequently performed in the digital domain to differentially eliminate line noise and column noise generated within the imaging System-on-Chip. By providing information between the sub-blocks, the algorithms can converge more quickly. The technique enables multiple signal paths to separately handle individual colors and to increase imaging data throughput.

Apparatus and method for stabilizing image sensor black level

A data switch includes multiple switching modules interconnected over a backplane. The data switch maintains flow integrity while path transitioning. The flow integrity can be maintained by temporarily disabling one or more of the switching modules from transmitting data units over the backplane for a flow undergoing a path transition. The disable condition is imposed when the path transition is commenced, and is lifted after the path transition is completed and an interval has passed ensuring that all data units for the flow transmitted to the backplane prior to imposing the disable condition have cleared the backplane. The backplane includes a multicast fabric and a unicast fabric, wherein flow path transitions are made from the multicast fabric to the unicast fabric upon source learning. All switching modules are temporarily disabled from transmitting data units having as a destination address an address undergoing source learning to the backplane.

Flow integrity for path transitioning data switch

An ATM switch with rate-limiting congestion control has a plurality of input ports, a plurality of output ports operatively associated with one or more data buffers, an output control and a switch fabric for switching data units from any of the input ports to any of the output ports on virtual connections. The ATM switch imposes and enforces transmission rate-limiting policies against the virtual connections when the backlog of data units for delivery to a particular output port reaches a particular level. The ATM switch may be arranged to exempt high priority data units from the imposed rate limitations and has a means to lift the rate limitations when the backlog has been sufficiently reduced.

ATM switch with rate-limiting congestion control

A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from 'empty' to 'not empty', or vice versa, rather than on a &#x201c;per cell&#x201d; request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from &#x201c;not clear to release&#x201d; to &#x201c;clear to release&#x201d;, or vice versa, rather than on a &#x201c;per cell&#x201d; grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is &#x201c;empty&#x201d; and the opposite binary value when the logical output queue's status is &#x201c;not empty&#x201d;. The status of each logical output queue is monitored at inputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is &#x201c;not clear to release&#x201d; and the opposite binary value when the logical output queue's status is &#x201c;clear to release&#x201d;. Outputs generate (but do not transmit) release grants in a logical order determined by running a grant generation algorithm. Inputs release discrete information units in a logical order determined by running a release algorithm. Status messages for logical output queues are re-transmitted when extra bandwidth is available to remove any inaccurate view of the status of the logical output queues resulting from transmission failures of the original status messages.

Input buffering and queue status-based output control for a digital traffic switch

The present invention, generally speaking, uses input buffering and output control to provide a high-speed, high-performance digital traffic switch. This approach solves all of the problems noted above with respect to the prior art (input buffering/input control, output buffering/output control). Dropped discrete information units (cells) are dropped at the input port, and so will not be transmitted across the switch fabric. This reduces the traffic load on the switch fabric during congested periods, and makes the switch fabric easier to design and expand. Input buffering/output control allows for the use of smaller buffers than output buffered/output control architectures for the same level of &ldquo;discrete information unit (cell) drop&rdquo; performance, and scales well to larger systems. Input buffering/output control provides all the information necessary to the output (data flow) controller necessary to implement very precise control algorithms. These algorithms can then administer switch fabric admission polices and contract enforcement fairly across all input ports.

Input buffering/output control for a digital traffic switch

A digital traffic switch having DIBOC buffer control has a queue status-based control strategy to limit status traffic on the switch and status buffer requirements. Status messages are transmitted from inputs to outputs when the content status of a logical output queue has changed from &ldquo;empty&rdquo; to &ldquo;not empty&rdquo;, or vice versa, rather than on a &ldquo;per cell&rdquo; request basis. Status messages are transmitted from outputs to inputs when the clearance status of a logical output queue has changed from &ldquo;not clear to release&rdquo; to &ldquo;clear to release&rdquo;, or vice versa, rather than on a &ldquo;per cell&rdquo; grant basis. The status of each logical output queue is monitored at outputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is &ldquo;empty&rdquo; and the opposite binary value when the logical output queue's status is &ldquo;not empty&rdquo;. The status of each logical output queue is monitored at inputs by retaining and updating a single status bit which has a particular binary value when the logical output queue's status is &ldquo;not clear to release&rdquo; and the opposite binary value when the logical output queue's status is &ldquo;clear to release&rdquo;. Outputs generate (but do not transmit) release grants in a logical order determined by running a grant generation algorithm. Inputs release discrete information units in a logical order determined by running a release algorithm. Status messages for logical output queues are re-transmitted when extra bandwidth is available to remove any inaccurate view of the status of the logical output queues resulting from transmission failures of the original status messages.

The present invention, generally speaking, uses input buffering and output control to provide a high-speed, high-performance digital traffic switch. Dropped discrete information units (cells) are dropped at the input port, and so will not be transmitted across the switch fabric. This reduces the traffic load on the switch fabric during congested periods, and makes the switch fabric easier to design and expand. Input buffering/output control allows for the use of smaller buffers than output buffered/output control architectures for the same level of 'discrete information unit (cell) drop' performance, and scales well to larger systems. Input buffering/output control provides all the information necessary to the output (data flow) controller necessary to implement very precise control algorithms. These algorithms can then administer switch fabric admission polices and contract enforcement fairly across all input ports.

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Calabasas, CA, United States of America

John Daniel Wallner