Hewlett-packard Development Company, L.p.

Hewlett-packard Company

John D Wanek

Samuel D Naffziger

Norman H Chang

Rex Petersen

Jon Eric Josephson

Jeremy Glen Slade

An interactive repeater insertion simulator (IRIS) system and method quickly and easily optimize the design of an integrated circuit (IC) interconnect for an electrical signal through the insertion of repeaters. The IRIS system utilizes the combination of a router, a repeater inserter, and a delay simulator to efficiently simulate repeater insertion. The router defines the route between more than one circuit and derives a first netlist. The first netlist is then sent to the repeater inserter to define the insertion of repeaters. A second netlist is outputted from the repeater inserter having thereupon one or more repeaters, inserted, and the physical locations of these repeaters along the interconnect for optimal performance, and minimum propagation delay. The delay simulator is then run on the second netlist to calculate the new interconnect delays. The interconnect delays may then be plotted or otherwise output for examination.

Interactive repeater insertion simulator (IRIS) system and method

A method of designing a VLSI chip and a chip designed according to the method are described. The method includes the steps of early consideration of resistive and capacitive values during a VLSI chip design process. The method provides for estimation of signal routes between nodes of functional blocks to be incorporated in the chips. The estimation may be based on a floor plan describing the positioning of the functional blocks, a connectivity description identifying connections between ports of the blocks and physical and mechanical configuration parameters. The functional blocks and design of the layout may be hierarchical in nature. The signal route estimation may be based on control factors such as the specification of signal route establishment algorithms. The next step is to foliate the nodes followed by determining resistance and capacitance values corresponding to all or parts of the estimated signal routes. The resistive and capacitive values may be incorporated into a model and a connectivity net list may be generated.

Resistance and capacitance estimation

The present invention includes a system for and a method of determining noise characteristics of a circuit of an integrated circuit. The circuit is classified based on its topology and measured circuit parameters. Noise characteristics are retrieved using the circuit classification and circuit parameters to calculate a noise response. Classification and characterization may be performed on each individual input.

System and method of determining the noise sensitivity characterization for an unknown circuit

The present invention includes an apparatus and a method of designing integrated circuits in which the susceptibility of the integrated circuit to noise is estimated by analyzing the components of the circuits. Suspected noise susceptibility factors were investigated to determine the effects of various potential factors on noise characteristics. It was determined that percent of &ldquo;bad&rdquo; capacitance to total capacitance of wire coupling pairs of components, the total length of the corresponding wires between pairs of components that are subject to capacitive coupling and driver output impedance of driving circuits each contributed significantly to noise factors in integrated circuits. It was also determined that the integrated circuit being analyzed can be analyzed as pairs of coupled components (drivers, receivers an interconnections between drivers and receivers) to which the noise susceptibility factors can be applied and used to determine the overall susceptibility of noise of the circuit.

System and method of determining the noise sensitivity of an integrated circuit

A simultaneous path optimization (SPO) system determines where to insert repeaters within interconnects of an integrated circuit (IC) during the design of the interconnects in order to ultimately reduce signal propagation delays in the interconnects. The SPO system is designed as follows. A netlist of an electrical network is obtained. The netlist is simulated with a delay simulator to determine delays from a source to each sink. A slack parameter for each branch of the network is determined. The slack parameter is computed for each branch by subtracting a signal propagation delay associated the each branch from a timing constraint associated with each branch. The SPO system determines a main branch in the network as one of the branches that exhibits the largest one of the slack parameters. A total slack parameter is determined by adding the slack parameters. The SPO system determines how many of the repeaters, if any, should be inserted in side branches extending from the main branch by simulating repeaters in the side branches and determining whether the total slack parameter decreases by insertion of the repeaters. The SPO system determines how many repeaters, if any, should be inserted along the main branch using a delay simulator. Optionally, the SPO system may further determine how many more of the repeaters, if any, should be inserted in the side branches using a delay simulator. Finally, the SPO system outputs the repeater locations and connectivity.

Simultaneous path optimization (SPO) system and method

A method and system for determining locations of interconnect repeater farms in the physical design of an integrated circuit is presented. The optimal unconstrained repeater locations are calculated for a given routing list of interconnect nets. Repeater farms are defined in areas of concentration of the calculated optimal unconstrained repeater locations. The optimal constrained repeater locations are then calculated such that the repeater locations are constrained to the repeater farms. A set of sub-optimal interconnect nets which are hurt the most from the repeater farm constraint are selected. The optimal unconstrained repeater locations for the selected set of sub-optimal interconnect nets are then calculated and additional repeater farms are defined to encompass areas of concentration of the optimal repeater locations of the sub-optimal interconnect nets. The process is repeated until desired performance gain is achieved.

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Denver, CO, United States of America

John D Wanek