Standard Microsystems Corporation

John D Virzi

Richard Wahler

Ronald W Streiber

Raphael Weiss

Robert W Schoepflin

Randy B Goldberg

Ariel Hendel

Rajiv Deshmukh

Donald D Noviello

Richard H Boz

A resistor/capacitor identification detection (RCID) circuit may provide system level identification of hardware (e.g. circuit board ID) through a single pin interface, by identifying up to a specified number of more than two quantized RC time constant states by measuring the discharge and charge times of an external RC circuit coupled to the single pin. The RCID circuit may initiate the discharge followed by a charging of the external RC circuit. The signal developed at the signal pin may be provided to the input of a threshold detector, with the threshold set at a specified percentage of a supply voltage used for operating the RCID circuit. The digitized output of the threshold detector may be used to gate a counter, after having been filtered through an input glitch rejection filter. A resolution of the counter may be determined by a high frequency clock used for clocking the counter. The numeric values of the charge and discharge times may be stored in data registers comprised in the RCID circuit.

Resistor/capacitor based identification detection

A double buffered flash bank. In one embodiment, a flash interface may be programmed by a register interface with a first set of data while a second set of data is being written to the register interface. In one embodiment, flash banks may be programmed in parallel using latched register interfaces. For example, while data from a first register interface is being written to the first flash bank and data from a second register interface is being written to a second flash bank, new data may be written to the first register interface and to the second register interface. The new data may then be written from the first register interface to the first flash bank and from the second register interface to the second flash bank.

Double buffered flash programming

A method and apparatus for hot-docking is disclosed. In one embodiment, a portable computer system includes a bus bridge and a bus coupled to the bus bridge. The bus may have one or more peripheral devices or peripheral interfaces coupled to it. The bus may also be coupled to a docking interface having a bus switch. The bus switch, when closed and the computer is coupled to a docking station, may couple the bus to a peripheral interface in a docking station. The bus switch may close responsive to docking, thereby completing the electrical coupling of the bus to the peripheral interface in the docking station. The closing of the bus switch may be controlled by the docking interface such that operations on the bus are not interrupted during the docking procedure.

Switchable hot-docking interface for a portable computer for hot-docking the portable computer to a docking station

A circuit and technique whereby loopback testing is performed in a serial communications device by concurrently transmitting from and receiving data into a single FIFO storage unit. The circuit includes a transmitter, a receiver, a single FIFO, operatively connected to both the transmitter and the receiver, for storing both transmitted and received data at the end of a loopback test. The circuit may be part of a transceiver which may in turn be part of an infrared communications controller installed in a personal computer.

Loopback transmission testing in a communications device

Method and apparatus are provided for data communication control within the communication controllers of stations within a local area network. In general, the method and apparatus involves maintaining within the command and status control interface unit of the communication controller, receive and transmit command queues as well as receive and transmit status queues. Pluralities of receive and transmit data packet storage locations are provided for storing data packets to be received as well as transmitted. Each receive command is uniquely associated with a data packet storage location. Receive and transmit commands are buffered in a pipeline manner in the receive and transmit command queues, respectively, whereas receive and transmit status bits are buffered in a pipeline manner in the receive and transmit status queues, respectively. The processor interfacing with the communication controller buffers transmit and receive commands in their respective queues and allocates corresponding data packet storage locations for these commands. The media access control unit of the communication controller executes each command when it is ready according to network protocol, and generates status bits which are buffered in respective status bit queues. The status bits are selectively processed to generate interrupts to the host processor, which can be serviced in due course. As a result of the present invention, consecutive transmission and reception of data packets can be achieved in a manner independent of the operation of the host processor. Consequently, the minimum back-to-back separation between two communication events of the same type, is eliminated thereby improving node and network data throughout.

Method and apparatus for controlling data communication operations

A controller for use in a local area network includes an arbitration circuit that permits data communication between a processor and a buffer memory associated with the controller to take priority over data communication between controller and buffer memory. The arbitration circuit interrupts a controller-initiated read or write cycle upon the receipt of a read or write memory access request from the processor.

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Bayside, NY, United States of America

John D Virzi