Advanced Micro Devices Corporation

John D Spano

John Lee Nistler

A metallization system ( ) suitable for use in a semiconductor component and a method for fabricating the metallization system ( ). The metallization system ( ) includes a dielectric material ( ) disposed on a major surface ( ) of a substrate ( ). The dielectric material ( ) contains a dielectric filled plug ( ) over a conductor ( ). A metal filled plug ( ) extends through the dielectric filled plug ( ). The metal of the metal filled plug ( ) electrically contacts the conductor ( ). The metallization system ( ) may be fabricated by etching a via ( ) in the dielectric material ( ) and filling the via ( ) with a dielectric material ( ) having a dielectric constant that is greater than the dielectric constant of the dielectric material ( ) disposed on the major surface. A via ( ) is formed in the dielectric material ( ) that fills the via ( ) and the via ( ) is filled with a metal.

Metallization system for use in a semiconductor component

The present invention is directed to a method and system for testing a plurality of integrated circuits. According to one embodiment of the invention, a method and system for testing a plurality of integrated circuits using a probe card having a plurality of circuit sites is provided. First, a group of the plurality of integrated circuits is associated with the probe card and a first-pass test is performed in parallel on each associated integrated circuit in the group using a first number of signal channels for each circuit site. A particular one of the integrated circuits in the group which passed the first-pass tests is then selectively associated with a particular one of the circuit sites, and a second-pass test is performed on the particular one integrated circuit using a second number of signal channels greater than the first number. In this manner, the use of test system resources may be optimized with expensive second-pass tests (e.g., performance tests) only being performed on circuits passing less-expensive first-pass tests (e.g., BIST and scan tests).

Parallel test method

A method for partial parallel testing a plurality of integrated circuit packages using a multi-package tester head having a plurality of sockets. Each socket is used for testing an integrated circuit package. A first one of the sockets has a full complement of signal channels, and the other sockets have exclusive subsets of the full complement of signal channels. The first socket and the other sockets support parallel testing of the integrated circuit packages according to a first type of test. Only the first socket, with its full complement of signal channels, supports a second type of test. To test a plurality of integrated circuit packages, a group of packages are inserted in the sockets. A first-pass test is then performed, in parallel, on the packages in the sockets. Then, for packages that passed the first-pass test, second-pass testing is performed sequentially using the first socket.

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Austin, TX, United States of America

John D Spano