Martin Marietta Corporation

Lockheed Martin Corporation

Synopsys, Inc.

John D Lofgren

Richard W Benton, Sr

H Ray Kelley

William A Pearson

Brett W Attaway

Brett Kobernat

James A Thorne

One embodiment of the present invention provides a system for augmenting a pipeline with a bubble-removal circuit. During operation, the system generates a bubble-removal circuit which determines a clock-enable signal based at least on whether an upstream register has valid data and whether the pipeline is stalled. Next, the system gates the clock signal using the clock-enable signal. The augmented pipeline can determine whether a first register contains invalid data, which is associated with a bubble. Next, the augmented pipeline determines whether a second register contains valid data, wherein the second register is adjacent to and upstream from the first register. If the first register contains invalid data and the second register contains valid data, the augmented pipeline replaces the invalid data of the first register with valid data based on the valid data in the second register without propagating the invalid data to a downstream register.

Method and apparatus for augmenting a pipeline with a bubble-removal circuit

One embodiment of the present invention provides a system that removes a bubble from a pipeline. During operation, the system first detects a stall in the pipeline. The system next determines whether a first register contains invalid data, which is associated with a bubble. Next, the system determines whether a second register contains valid data, wherein the second register is adjacent to and upstream from the first register. If the first register contains invalid data and the second register contains valid data, the system replaces the invalid data of the first register with valid data based on the valid data in the second register without propagating the invalid data to a downstream register. As a result, the system removes the invalid data from the pipeline.

Removing a pipeline bubble by blocking clock signal to downstream stage when downstream stage contains invalid data

A built-in self test architecture for testing one or more integrated circuits. Each circuit is provided with an interface compatible with IEEE standard 1149.1 and one or more scan registers containing scan cells for supplying input test data to, and receiving output test data from, the internal circuitry of the integrated circuits, a pseudo-random pattern generator for supplying patterns of test data to the boundary scan register, and a pattern compressor for compressing the output test data into a signature. The architecture also includes a single clock multiplexer, located external to the integrated circuits, for selectively supplying a system clock or a test clock to the testing components of each integrated circuit.

Fast bist architecture with flexible standard interface

A digital signal processing system which uses an input image including a plurality of pixels to establish boundaries of objects in the input image. Each of the pixels has a gradient value and the object includes a centroid. Using a segmentation process, the digital signal processing system decides on a perimeter surrounding the object in the input image and then repeatedly searches for a pixel having the highest gradient value and marks that pixel having the highest gradient value as an edge pixel of the object.

Methods and apparatus for centroid based object segmentation in object

A memory controller includes an input data path and an output data path. First circuitry generates signals to put the input data into at least one variably-dimensioned logical array of memory cells of a memory. Second circuitry generates signals to extract from the memory the contents of at least one variably-dimensioned logical array of memory cells. The memory may be double buffered such that data input to one of the portions may take place simultaneously as data output from the other of the portions. In a preferred embodiment, any combination of up to 254 total variable-dimensioned logical arrays of memory cells may be defined for input to and output from the memory. The memory controller may be viewed as supporting two simultaneous processes, an input 'windowing' process for receiving windows of data and an output 'windowing' process for simultaneously passing out windows of data. The memory controller is preferably realized in the form of a monolithic integrated circuit employing 'bit-slice' architecture and is static and dynamic RAM-compatible.

Versatile memory controller chip for concurrent input/output operations

A testing device has an architecture including a board test interface for coupling to test points on a circuit board; a programmable processor, coupled to the board test interface, for controlling a test of the circuit board via the board test interface; and a first communications interface, coupled to the programmable processor, for coupling to a like first communications interface located on another testing device. The programmable processor uses the first communications interface for communicating test commands and test results with the other testing device, so that a complete test of a system can be produced. The testing device may further include a control port, coupled to the programmable processor, for communicating system test commands between a host processor and the programmable processor. In response to a first system test command received from the host processor via the control port, the programmable processor may use the first communications interface to send a second test command to another testing device. Also, a number of identical testing devices, each located on a corresponding one of a number of circuit boards in a system, may use the first communications interface to transmit test results to one of the testing devices, designated as a master coordinating device. The master coordinating device then forwards all of the test results to a host processor for analysis. The entire testing device may be fabricated as a single integrated circuit, in order to provide great testability without occupying a great deal of circuit board space.

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Orlando, FL, United States of America

John D Lofgren