Inmos Limited

John D Heightley

Kim Carver Hardee

Rahul Sud

A static RAM (random access memory) is described wherein fully asynchronous active equilibration and precharging of the RAM's bit lines provides improved memory access time and lower active power dissipation. In the preferred embodiment, each change in the memory's row address is sensed for developing a clock pulse of a controlled duration. The clock pulse is received by a group of equilibrating transistors and a group of precharging transistors which are coupled to the memory's bit lines. When the clock pulse occurs, all the abovementioned transistors conduct to effect simultaneous equilibration and pre-charging of the bit lines.

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Monument, CO, United States of America

John D Heightley