Promos Technologies, Inc

Mosel Vitelic Corporation

Other

John D Heightley

Jon Allan Faue

Kim Carver Hardee

Sargent S Eaton, Jr

Steve Eaton

Lawrence Lee Aldrich

A configurable architecture, hybrid analog/digital delay locked loop and technique with fast open loop digital locking for integrated circuit dynamic random access memory (DRAM) devices and devices incorporating embedded DRAM. The DLL design and technique disclosed employs a hybrid analog/digital delay line, but does not use conventional closed loop architecture during the digital phase of the locking process.

Configurable architecture hybrid analog/digital delay locked loop (DLL) and technique with fast open loop digital locking for integrated circuit devices

A circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices in which only N-channel current regulating transistors are used in the voltage-controlled inverters and both the rising and falling edges can be adjusted by cascading two such inverters. The potential for cascading of these inverters allows for additional accuracy to be achieved.

Circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices

A DLL circuit uses a rising edge DLL to align the rising edge of the output data to the system clock and a falling edge DLL to align the falling edge of the output data. The DLL circuit does not use the falling edge of the input clock to provide a reference for the falling edge DLL. The DLL circuit uses the rising edge of a first reference clock (a buffered version of the input clock) to align the rising edge of the output data. An additional DLL is used to generate a precise second reference clock that is delayed by exactly one-half period of the first reference clock to align the falling edge of the output data. Any variation in the duty cycle of the input clock or the input clock buffer does not effect the duty cycle of the output data.

Use of multiple voltage controlled delay lines for precise alignment and duty cycle control of the data output of a DDR memory device

An equalization circuit for a pair of resistive-capacitive data lines includes primary and secondary equalization circuits attached at both ends of the data line pair. A primary equalization circuit at one end of the data line pair receives a primary control signal, and a secondary equalization circuit at the other end of the data line pair receives a secondary control signal, which is different than the primary control signal. The equalization devices in the primary equalization circuit are attached near the read and write amplifiers and operate normally since all the information is available as to whether or not the corresponding data line pair should be equalized. The additional equalization devices in the secondary equalization circuit placed at the other end of the data line pair receive a simpler control signal that lacks the information as to whether or not any particular data line pair is being equalized.

Dual equalization devices for long data line pairs

A differential amplifier design and bias control technique of particular applicability for low voltage operation in which the threshold voltage of n-channel differential input transistors is controlled using substrate bias in order to allow a wider range of input signal levels. Further disclosed is a technique for controlling the substrate bias of the input transistors of a differential amplifier based on the level of the output of the amplifier in addition to a differential amplifier circuit capable of low voltage operation in which an additional bias current is introduced that enables the output pull-up current to be increased without increasing the pull-down current, as well as circuitry for optimizing the performance of the differential in both DDR-I and DDR-II operational modes.

Low voltage differential amplifier circuit for wide voltage range operation

A differential amplifier design and bias control technique of particular applicability for low voltage operation in which the threshold voltage of n-channel differential input transistors is controlled using substrate bias in order to allow a wider range of input signal levels. Further disclosed is a technique for controlling the substrate bias of the input transistors of a differential amplifier based on the level of the output of the amplifier in addition to a differential amplifier circuit capable of low voltage operation in which an additional bias current is introduced that enables the output pull-up current to be increased without increasing the pull-down current.

Low voltage differential amplifier circuit and a sampled low power bias control technique enabling accommodation of an increased range of input levels

An analog delay locked loop for receiving a reference clock signal and for generating a delayed output clock signal includes a voltage controlled delay line, a fixed delay line, a delay voltage control, a fast/slow latch, a phase detector, as well as reset and clock off circuits. The fast/slow latch generates three signals that are received by the delay voltage control: a 'latched slow signal', a 'latched fast signal', as well as a &#x201c;latched fast to slow signal&#x201d;. The phase detector generates &#x201c;go fast&#x201d; and &#x201c;go slow&#x201d; signals that are received by the fast/slow latch. The analog delay locked loop sets the initial delay of the delay line at or near its minimum value on start-up. The delay is then forced to increase from the minimum value until a locking condition is achieved independent of the phase relationship between the reference and delayed clock signals.

Voltage-controlled analog delay locked loop

Low voltage differential amplifier circuit and bias control technique enabling accommodation of an increased range of input levels

A multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output (&ldquo;I/O&rdquo;) assignments in an integrated circuit memory device. By using non-uniform blocks of multiple identical sub-arrays, non-uniform assignments of blocks to banks and/or non-uniform assignments of I/Os to blocks, it is possible to optimize the dimensions of the chip and the placement of the I/Os with respect to the package pads. In this manner, the granularity of the building blocks of sub-arrays is improved while the flexibility in I/O assignment is also improved leading to more efficient and flexible chip layouts.

Multi-bank memory array architecture utilizing topologically non-uniform blocks of sub-arrays and input/output assignments in an integrated circuit memory device

A system and method for eliminating pulse width variations in digital delay lines partitions a delay line into two substantially identical blocks of delay inverters, inserting a first inverter between the two blocks and a second substantially identical inverter at the output of the second block. The requirement for matching device characteristics at the individual delay inverter level is eliminated and the only requirement is that the parasitic loading of the inverter between the blocks and the inverter on the output of the second block be the same. Consequently, the layout of the delay inverters in a single block may be made in the most efficient manner possible and the same identical layout can be used for the first and second blocks.

System and method for eliminating pulse width variations in digital delay lines

A read data latch circuit that provides a level shift between internal and external voltages that does not require added circuitry dedicated to equalizing or level shifting the data latch nodes. Data lines are provided having a higher capacitance than the capacitance of the data latch nodes. The data latch nodes are connected to the data lines through a switch. When the switch is open, an equalization charge is shared between the data lines and the latch nodes. The voltage for providing the equalization charge and data signals internal to the chip is lower than the data output signals provided to external circuitry by the data latch.

Dynamic data amplifier with built-in voltage level shifting

A read data latch circuit that requires only two phases to execute a data read cycle. The date read lines and data latch lines are precharged and equalized during the data read cycle. A separate phase for equalizing the data latch nodes is eliminated. Rather, the data latch nodes charge share with the previously equalized and precharged data lines. The latch nodes are effectively precharged and equalized, as the capacitance on the data lines is much larger than the capacitance on the data latch nodes.

Two-phase charge-sharing data latch for memory circuit

A system and method for supporting sequential burst counts of particular utility with respect to double data rate (&ldquo;DDR&rdquo;) synchronous dynamic random access memory (&ldquo;SDRAM&rdquo;) devices wherein each memory bank is divided into halves, corresponding to Even (AO &equals;0) and Odd (AO &equals;1) portions. Separate address busses may be provided for those bits necessary to accommodate the maximum burst length. As the column addresses are loaded, the buffers associated with the Even bus check to determine if the pad address &ldquo;Y&rdquo; or &ldquo;Y&plus;1&rdquo; should be loaded. Loading &ldquo;Y&plus;1&rdquo; is necessary to support sequential counting if the start address is Odd (AO &equals;1). &ldquo;Y&rdquo; selects in the Odd and Even banks are then selected and incremented, concurrently. Nevertheless, the Even field is always &ldquo;Y&plus;1&rdquo;, that is, Y &equals;Y &plus;1. In operation, the present invention advantageously loads the &ldquo;Even&rdquo; section of the bank with &ldquo;Y&plus;1&rdquo; initially (if required), then the first access, and all subsequent ones, continue with no knowledge that the &ldquo;Y&rdquo; address in the &ldquo;Even&rdquo; field is different from that in the &ldquo;Odd&rdquo; field. By means of the load circuit disclosed herein, Odd and Even column paths are also effectively electrically the same resulting in no appreciable difference in critical timing or substantial path layout differences.

System and method for supporting sequential burst counts in double data rate (DDR) synchronous dynamic random access memories (SDRAM)

A system and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line such as those used in delay-locked loop (&ldquo;DLL&rdquo;) circuits in integrated circuit (&ldquo;IC&rdquo;) devices such as double data rate (&ldquo;DDR&rdquo;) dynamic random access memory (&ldquo;DRAM&rdquo;), static random access memory (&ldquo;SRAM&rdquo;), processors and other IC devices. The technique renders the incremental changes for each correction to the control voltages to the voltage controlled delay line a function of the control voltage itself. The change in the control voltage becomes smaller as the control voltage gets lower thereby effectively precluding over-correction and excessive jitter. Since the smallest corrections to be made will occur when the control voltage is much lower than its initial value, the majority of the corrections made in moving from the initialization point to the final lock point in the DLL loop will be much larger than the final corrections thereby resulting in only minimally slower locking times than would otherwise be the case. The changes in delay become inherently smaller if the lock point is at a higher VR value.

System and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line

An architecture for a high speed memory circuit having a relatively large number of internal data lines is shown to include global read and write data lines, and power and ground lines extending laterally across the array. The laterally extending lines are preferably within the third layer of metal. Preferably, the only other metal interconnect over the memory arrays is in the first metal layer, which is used to strap the word lines. Sense amp bands extend longitudinally along the borders of each memory cell bank. Local read and write data lines and read and write column select lines extend through the sense amp bands. Power and ground lines also extend through each sense amp band. Preferably, the architecture includes read path circuitry including a local read circuit that selectively isolates the global read data lines from the local read data lines. The architecture also preferably includes write path circuitry including a local write circuit that selectively isolates the global write data lines from the local write data lines. This architecture results in relatively low capacitance on the global read and write data lines, which permits faster data transfer speed with lower power requirements. It also results in relatively low resistance power and ground bussing, which further reduces the power requirements of the memory circuit.

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Colorado Springs, CO, United States of America

John D Heightley