Hewlett-Packard Company

Agilent Technologies, Inc.

John D Hansen

Stan W Bowlin

Arnold S Berger

Lewis S Kootstra

Beth V Jones

William Fleck

Justin S Morrill, Jr

Adrian M Hernandez

John J Sinnott

A data acquisition circuit and method according to embodiments of the invention insert overflow states into a data storage unit among samples of input data and associated time tags that are of interest. The overflow states allow multiple overflows of the time tags without intervening samples of input data being stored, thus allowing the infrequent capture of samples of the input data while maintaining accurate timing data. Also, the overflow states obviate the need to store an overflow status flag with each stored sample of input data and time tag in the data storage unit.

Acquisition unit and method for infrequent capturing of data samples with associated timing information

A system for coordinating the measurement activity of a plurality of emulators and their associated internal analyzers uses a bus with three signal lines. A READY signal is set false by any emulator that initiates a break (a transition from running user code to running a monitor). The READY signal is set false by the breaking emulator at the very beginning of its break, without waiting for the resumption of the monitor program. The false ready signal is detected immediately by the other emulators, which then break in sympathy. The READY signal is further used to restart all emulators in unison. The emulator that initiated the break remains running its monitor, while the others start their monitors, determine that they did not cause the break, and then in anticipation of a restart, essentially suspend their monitors and prepared to start running user code. As each emulator becomes ready it releases the READY signal. As the last emulator becomes ready, it too releases READY, which then does true. At this all emulators complete their escape from their monitors (which for each of them amounts to just an instruction fetch, or so) and resume execution of their user code.

Method and apparatus for coordinating measurement activity upon a

A system for coordinating the measurement activity of a plurality of emulators and their associated internal analyzers uses a bus with three signal lines. A READY signal is set false by any emulator that initiates a break (a transition from running user code to running a monitor). The READY signal is set false by the breaking emulator at the very beginning of its break, without waiting for the resumption of the monitor program. The false ready signal is detected immediately by the other emulators, which then break in sympathy. The READY signal is further used to restart all emulators in unsion. The emulator that initiated the break remains running its monitor, while the others start their monitors, determine that they did not cause the break, and then in anticipation of a restart, essentially suspend their monitors and prepare to start running user code. As each emulator becomes ready it releases the READY signal. As the last emulator becomes ready, it too releases READY, which then goes true. At this all emulators complete their escape from their monitors (which for each of them amounts to just an instruction fetch, or so) and resume execution of their user code. A four-state state machine in each emulator assists in this, and is in part, advanced through its states by transitions in the READY signal. The four states correspond to: running the monitor, ready to start executing user code, executing user code, and invoking the monitor. A TRIGGER signal is available to allow analyzers to trigger other analyzers, or to cause an emulator to break. An EXECUTE signal is available to allow a single command issued to any emulator to cause target system starts from preselected initial conditions.

Data processing systems for coordinating measurement activity upon a

A data capture circuit for a logic state analyzer includes a qualifier pattern comparator circuit that responds to a collection of input qualifier signals by producing a number of qualifier pattern signals each representative of the occurrence of a preselectable pattern in the input qualified signals. A like number of clock detection circuits each responds separately to the values of separate clock signals by producing separate qualified clock signals, each of the like number of which represents the simultaneous occurrence of a preselected transition in each particular clock signal and of a qualifier pattern signal associated with that clock signal. The several separate qualified clock signals generally occur at separate times, and each is used to individually capture into several temporary storage registers separate collections of data signal values occurring at those separate times. A master clock selection means allows the user to designate as a master clock signal a qualified clock signal that is expected to occur not earlier in sequence than the others. The master clock signal causes transfer of the contents of the temporary storage registers into intermediate storage registers whose outputs are then merged and combined by subsequent and simultaneous forwarding as a single parallel entity to the main data memory of the logic state analyzer, while at the same time the temporary storage registers are freed to capture fresh data.

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Colorado Springs, CO, United States of America

John D Hansen