International Business Machines Corporation

John D Chickanosky

Robert L Barry

Michael Richard Ouellette

Steven Frederick Oakland

A highly functional built in self test circuit for embedded compiled macros is useful for testing embedded compiled macros having differing parameters. The built in self test circuit receives a scan vector that describes the parameters of the embedded compiled macro that is to be tested. For, example, the number and width of words stored in a read only memory (ROM) are scanned into the built in self test circuit for controlling the test sequences. A state machine within the built in self test circuit cycles through test vector generation, test vector application, data output scanning and compression for signature analysis. Parallel outputs of the embedded compiled devices are serialized so that regardless of the number of outputs, a serial input shift register can be used for signature generation.

Serial input shift register built-in self test circuit for embedded

A growable read only memory (ROM) provides improved performance over a wide range of array sizes by incorporating a localized reference bitline that accurately tracks changes in loading and variations in process parameters. The reference bitline is input into one side of a differential sense amplifier while a selected data bitline is input into the other side. The reference bitline is precharged and includes two columns, a first column includes devices that are matched to memory cell devices wherein a device of the selected word line will be selected to discharge the referenced bitline. The second column includes a recessed oxide device corresponding to each memory cell in the column. The combination of the two columns ensures that the reference bitline will discharge at a predetermined rate that tracks the rate at which a selected contact programmed memory cell discharges.

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South Burlington, VT, United States of America

John D Chickanosky