Apple Inc.

Silicon Image Gmbh

Koninklijke Philips Corporation N.v.

Lattice Semiconductor Corporation

John D Banks

Albert M Scalise

Paul Daniel Wolf

Eric N Lee

Gijung Ahn

Seung Ho Hwang

Stephen J Keating

Duane P Siemens

Keewook Jung

Kenneth Mark Karakotsios

James D Lyle

Adrian Sfarti

Michael Schumacher

Vladimir Grekhov

Duane Siemens

Michael Anthony Schumacher

In some embodiments, a device includes a bus, a parallel source, and a parallel sink. The parallel source is to provide parallel groups of signals including video signals to the bus, wherein the bus has a number of lanes that is fewer than a number of signals used to represent a pixel such that pixels are represented in more than one of the parallel groups. The parallel sink is to receive the parallel groups of signals from the bus, wherein the parallel sink includes a signal extractor to separate at least a portion of the groups of signals into multiple channels, and encoder and serializer circuits to encode and serialize the separated signals. Other embodiments are described and claimed.

Parallel interface bus to communicate video data encoded for serial data links

A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e.g., video, audio, and optionally also other auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one or more channels of the link during data islands between bursts of encoded video data, a pixel clock is transmitted over the link, and the receiver regenerates a clock for the audio data using time code data in the packets and the pixel clock. Other aspects of the invention are transmitters for transmitting encoded data and a pixel clock over a serial link, receivers for receiving such data and pixel clock and performing audio clock regeneration, and methods for transmitting encoded data and a pixel clock over a serial link and performing clock regeneration using the transmitted data and pixel clock.

Method and apparatus for regenerating a clock for auxiliary data transmitted over a serial link with video data

A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e.g., video, audio, and optionally also other auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one or more channels of the link during data islands between bursts of encoded video data. Other aspects of the invention are transmitters for use in encoding data for transmission over a serial link, receivers for receiving such data, and methods for sending encoded data over a serial link.

Method and system for video and auxiliary data transmission over a serial link

A bi-directional data path apparatus coupled between a first bus and a second bus for allowing a plurality of data transfering devices contained on either one of the buses to transfer data to the devices contained on the other bus. The data path apparatus includes latching stations designed to receive data from the first and second buses. The data path apparatus includes a plurality of byte lanes interconnecting the byte latching stations. A control mechanism directs the transfer of data along specific byte lanes and in a specific temporal order depending on the databus size of the devices sending and receiving data.

Data path apparatus for IO adapter

A bi-directional bus adapter coupling a system bus, which operates at a first speed using a first protocol, and an IO bus, which operates at a second speed using a second protocol, and allowing data transfering devices on either bus to transfer data to or from devices on the other bus. The bus adapter includes a cycle generation mechanism which is responsive to data cycles from one of the buses in order to generate bus cycles needed to complete a data transfer to a device on the other bus. The bus adapter includes a synchronization mechanism for converting the plurality of data cycles generated by the cycle generation mechanism from either the first speed to the second speed or vice versa. The bus adapter includes bi-directional data path mechanism for routing data between the system and IO buses according to said protocols, such that the data path directs bytes of data to specific data lines to perform byte steering and dynamic bus sizing on the data from the system bus to the IO bus. The bus adapter also includes a bi-directional address transceiver mechanism for routing addresses between said system and said IO buses.

IO adapter for system and IO buses having different protocols and speeds

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Cupertino, CA, United States of America

John D Banks