Associated Electrical Industries Limited

Gec-alsthom Limited

John D Ainsworth

David R Trainer

A switching control arrangement for a multilevel convertor minimizes the harmonic content of the converter voltage or current by an open-loop and/or a closed-loop control of the timing of the switching of the GTOs associated with the energy-storage components (e.g. capacitors) in the convertor. In a first open-loop arrangement the convertor current is quantized over its working range and different threshold values are provided in dependence on the quantization values of the current. In a second open-loop arrangement a continuous, non-quantized control is provided based on at least a quadratic approximation to the desired current-dependent behavior of the GTO switching angles. In a third, closed-loop arrangement, different GTO-switching threshold levels are provided as controlled by a Fourier integration process involving the nulling of those harmonics desired to be nulled. The control arrangement is applicable to chain or stacked-capacitor multilevel convertors and can be employed in SVC applications or applications in which the convertor draws real power as well as reactive power.

Switching control arrangement

A multilevel convertor having a set of series-connected capacitors and a set of associated series-connected switching elements employs a main control loop which controls some aspect of an AC system, e.g. busbar voltage, by controlling the switching times of the switching elements. The convertor also comprises one or more subsidiary control loops for establishing a desired relationship between mean DC voltage levels on the capacitors. The subsidiary control loops combine first signals proportional to DC voltage levels on the capacitors and second signals proportional to tap currents associated with the capacitor nodes to provide signals which modulate the timing of the switching of switching elements connected to those capacitors which are out of balance, while leaving alone the timing of the switching of switching elements associated with those capacitors which have the required voltage across them. The advantage of the invention is that it prevents the 'run-away' of individual capacitor voltages to values grossly in error, the run-away being due either to spontaneous instability or to temporary disturbances.

Multilevel converter with capacitor voltage balancing

A D.C. current transformer (used for measuring D.C.) comprising a common primary winding and a pair of saturable magnetic cores on which respective secondary windings are wound and connected in opposite series in series to a source of alternating e.m.f., is provided with phase-sensitive device for determining the sense of the unknown D.C. in the primary winding. The phase sensitive device periodically senses and integrates the voltage (whose waveform is the -45.degree. to +45.degree. portion of a sine wave) across at least one of the secondary windings. The sense of the integrated waveform depends on whether said voltage is initially positive or negative, and is determined by the sense of the unknown D.C. in the primary winding. Preferably said voltage is sensed at each half cycle of said alternating e.m.f.

D.C. current transformer circuits

A multi-loop control system for convertors of the kind used in h.v.d.c. transmission and industrial applications. The invention consists in a control circuit which effects transfer between two or more control loops, e.g. a constant-current loop and a constant .alpha. loop, in a smooth and precise manner, without extra smoothing lags, even in the presence of ripple in the controlled quantities.

Multi-loop control system for an ac/dc converter employing mode switching

A multi-phase inverter comprising a bridged array of thyristors periodically fired in sequence by a source of firing pulses has a circuit arrangement for controlling each extinction angle (.gamma.) of the thyristors individually. Said circuit arrangement comprises an adder for summing .gamma. signals and adder for differencing said sums to generate an error signal and, said error signal being applied to said source of firing pulses at appropriate phase angles to appropriate thyristors so as to tend to equalize said sums, the number of pairs of differenced sums being equal to the number of thyristors in the array. Preferably each error signal acts as a constant multiplier of a correction signal which is a harmonic of the A.C. output frequency of the inverter. The arrangement improves the efficiency by enabling each .gamma. to be minimized individually without risk of commutation failure.

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Stafford, United Kingdom

John D Ainsworth