Sun Microsystems, Inc.

Encore Computer U.s., Inc.

John D Acton

Chia Y Wu

Steven E Schelong

Steven P Kent

Jack M Hardy, Jr

Gavin G Gibson

Michael D Derbish

Hugh M Humphreys

William B DeRolf

Ricardo Yong

Charles D Binford

Daniel R Cassiday

Andrew W Wilson

Walter Timothy Nixon

Raymond J Lanza

Joel Vance Miller

Jonathan Broome

Mark Farabaugh

William M Hamilton, Iii

Lawrence C Grant

A plurality of PCIe switch complexes are interposed between a plurality of I/O devices and a plurality of microprocessor complexes. Each PCIe switching complex comprises a plurality of PCIe switches wherein each switch possesses at least one non-transparent port. The non-transparent port is used to cross-couple each PCIe switch creating an active matrix of paths between the HBAs associated with each I/O device and each microprocessor. The paths between each HBA (I/O device) and each microprocessor are mapped using a recursive algorithm providing each I/O device with direct memory access to each microprocessor.

Cross-coupled peripheral component interconnect express switch

Data buffering allocation in a microprocessor complex for a request of memory allocation is supported through a remote buffer batch allocation protocol. The separation of control and data placement allows simultaneous maximization of microprocessor complex load sharing, and minimization of inter-processor signaling/metadata migration. Separating processing control from data placement allows the location of data buffering to be chosen so as to maximize bus bandwidth utilization and achieve non-blocking switch behavior. This separation reduces the need for inter-processor communication and associated interrupts thus improving computation efficiency and performance.

Data buffer allocation in a non-blocking data services platform using input/output switching fabric

A method may involve: receiving an even number of odd-sized packets for transmission over a double data rate link; re-packetizing the even number of odd-sized packets into several even-sized packets; transmitting the even-sized packets over the double data rate link; and de-packetizing the even-sized packets to reform the even number of odd-sized packets. Re-packetizing may involve dividing each of the even number of odd-sized packets into an even-sized portion and a remaining portion. Each even-sized portion may be transferred as one of the even-sized packets. The remaining portions of each of the even number of odd-sized packets may be combined to form another one of even-sized packets. De-packetizing may involve associating each of several portions of one of the even-sized packets with a respective other one of the even-sized packets.

Transmitting odd-sized packets over a double data rate link

Various embodiments of systems and methods for performing write cache mirroring may involve accessing different mapped regions within a memory. The memory controller may automatically mirror write requests to another memory. Write requests targeting one mapped region may be verified such that local completion of the write indicates that the mirrored write has also completed. Write requests targeting another mapped region may be unverified. Unverified writes may be verified by performance of a verified write.

System and method for efficiently and reliably performing write cache mirroring

A method and system for managing cache levels based on battery backup level are described. In one embodiment, the method comprises measuring the level of charge stored in an exhaustible power source. The method further comprises monitoring the level of charge stored in the exhaustible power source. The method further comprises adjusting the storage level of the cache in response to a detected change in the level of charge. In this way, the method ensures that adequate battery power is available to transfer the contents of the cache to a non-volatile data storage medium.

Method and system for dynamically adjusting storage system write cache based on the backup battery level

A method may involve: receiving a request to perform a block write to a target device and data associated with the block write; buffering the data associated with the block write prior to completing the block write to the target device; storing an indication identifying a block address range of the block write; receiving a request to perform a read to the target device; and determining whether an address of the read is within the block address range of the block write identified by the indication. In some embodiments, such a method may allow the read to complete ahead of the block write dependent on whether the address of the read is within the block address range of the block write identified by the indication.

Write posting memory interface with block-based read-ahead mechanism

Various embodiments of systems and methods for implementing shared memory regions in a distributed shared memory system may involve implementing several different shared memory regions in each distributed shared memory node. Each node may reflect write access requests targeting those shared memory regions to one or more other nodes, depending on which shared region is targeted (e.g., requests targeting one region may be reflected to a single other node while requests targeting other regions may be reflected to more than one other node). A node's completion of the requested write access locally may be dependent on the completion of the write access in the other nodes, depending on which shared memory region is targeted.

System and method for implementing shared memory regions in distributed shared memory systems

Resources may be shared between multiple controllers configured to access those resources by associating a portion of a semaphore shared memory region with each different shared resource. Whenever a local write request to the portion of the semaphore shared memory region is detected by a memory controller, the memory controller may broadcast the write request to other remote memory controllers. The memory controller may delay performing a memory access to a local copy of that portion of the semaphore shared memory region until the other memory controllers have performed the write access to their copy of the semaphore shared memory region. The values stored in the semaphore shared memory region indicate which controller currently has access to the shared resource.

System and method for synchronizing access to shared resources

A method for operating a data processing system is provided. The method includes receiving a plurality of data segments, and for each of the plurality of data segments, generating an error correction code (ECC) corresponding to the data segment, said ECC providing at least one-bit error correction capability. Finally, an extended parity segment is calculated from the plurality of data segments and the corresponding ECCs, said extended parity segment including a parity segment calculated from the plurality of data segments and a parity ECC calculated from the corresponding ECCs.

XOR processing incorporating error correction code data protection

Each node's memory controller may be configured to send and receive messages on a dedicated memory-to-memory interconnect according to the communication protocol and to responsively perform memory accesses in a local memory. The type of message sent on the interconnect may depend on which memory region is targeted by a memory access request local to the sending node. If certain regions are targeted locally, a memory controller may delay performance of a local memory access until the memory access has been performed remotely. Remote nodes may confirm performance of the remote memory accesses via the memory-to-memory interconnect.

System and method for sharing memory among multiple storage device controllers

A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board. The printed circuit board includes a sensor for sensing when data is transferred into the directly sharable memory, a queuing device for queuing the sense data, a serializer for serializing queued data, a transmitter for transmitting serialized data onto the serial bus to a next successive processing node, a receiver for receiving serialized data from a preceding processing node, and a deserializer for transforming received serialized data into a parallel format.

Data processing system including a shared memory resource circuit

A data processing system includes a plurality of nodes, a serial data bus interconnecting the nodes in series in a closed loop for passing address and data information, and at least one processing node. In one construction, this processing node has a processor, a printed circuit board, a memory partitioned into first and second sections and a local bus connecting the processor, a block sharable memory section of the memory, and the printed circuit board. The local bus is used for transferring data in parallel from the processor to a directly sharable memory section of the memory on the printed circuit board and for transferring data from the block sharable memory to the printed circuit board. The printed circuit board includes a sensor for sensing when data is transferred into the directly sharable memory, a queuing device for queuing the sensed data, a serializer for serializing the queued data, a transmitter for transmitting the serialized data onto the serial data bus to the next successive processing node, a receiver for receiving serialized data from next preceding processing node, and a deserializer for deserializing the received serialized data into parallel data.

Computing system having multiple nodes coupled in series in a closed loop

Multiprocessor distributed memory system and board and methods therefor

A system for coupling sets of plurality of nodes that are memory coupled to pass write only data memory to memory via a data link that further includes an optical fiber controller coupled to each data link. Each controller is interconnected through fiber for high speed data transfers from one set of nodes to another. The controller is capable of connection implementing three and four cable interfaces. The data is transmitted through the fiber serially but the controller is adapted to receive parallel data and convert to serial form and vice versa.

Growing community of inventors

Plantation, FL, United States of America

John D Acton