Broadcom Corporation

John Cumming Leete

Hooman Darabi

Ahmad Mirzaei

Yuyu Chang

Wei Luo

Masoud Kahrizi

Bernd Pregardier

Walid Ahmed

Qiang Li

Behnam Mohammadi

Calvin (Shr-Lung) Chen

Xinyu Chen

Yiannis Kokolakis

Various configurations and arrangements of systems and methods for providing multi-carrier aggregation are described. A system in accordance with the disclosure can include a first mixer configured to receive a first signal in a first frequency band, a second mixer configured to receive a second signal in a second frequency band, a third mixer configured to receive the second signal in the second frequency band, and a fourth mixer configured to receive a third signal in a third frequency band. The system can further include a controller configured to selectively activate one of the first mixer and the second mixer, and selectively activate one of the third mixer and the fourth mixer.

Low cost and robust receiver architecture for down link carrier aggregation

A wireless communications transmitter is divided into N binary weighted communication signal processing paths including both fixed and variable gain communication signal processing chains. Specific bit sequences are used to select a combination of fixed and variable gain signal processing paths to adjust to a desired transmitter output power. Alternately, high and low power communication signal processing paths are chosen as needed with the high power communication signal processing path including an odd order harmonic notch filter.

Low voltage transmitter

An apparatus includes a dynamically configurable transformer configured to provide a gain to a target signal. The gain is dynamically configurable. The dynamically configurable transformer includes at least one parallel resistive element configured to be dynamically activated in parallel with a load.

Gain control using a dynamically configurable transformer

Methods and systems are provided to calibrate an oscillator circuit to reduce frequency pulling as a result of a change in power to a portion of the oscillator circuit. In an embodiment, an oscillator is coupled to a clock buffer circuit and a tuning capacitor configured to tune a frequency of the oscillator to a baseline frequency required for cellular communications. A change in power to the clock buffer circuit initiates a change in an amount of capacitance seen by the oscillator, which negatively impacts the tuning of the oscillator. A register stores a frequency offset caused by the change in power, and the tuning capacitor is adjusted, using the frequency offset, in response to the change in power, such that the total amount of capacitance seen by the oscillator is not changed when the change in power occurs.

Systems and methods for reducing frequency pulling in an oscillator circuit

An apparatus comprising: a baseband filter configured to produce a baseband signal utilizing an input signal; a mixer unit configured to produce an intermediate signal utilizing the baseband signal and a local oscillator signal; and a dynamically configurable transformer configured to provide a gain to the intermediate signal, wherein the gain is dynamically configurable.

Embodiments of an RF receiver front-end are presented herein. In an embodiment, the RF receiver front-end comprises a transconductance LNA, a passive mixer, and a g-enhanced common-gate buffer. The transconductance LNA is configured to convert an RF voltage signal to an RF current signal and provide the RF current signal at an output. The passive mixer is coupled to the output of the transconductance LNA and is configured to mix the RF current signal with a local oscillator signal to produce a frequency translated current signal. The g-enhanced common-gate buffer is configured to receive the frequency translated current signal at an input and convert the frequency translated current signal to a frequency translated voltage signal. In an embodiment, the input of the gm-enhanced common-gate buffer is configured to provide a low input impedance to limit a voltage swing of the frequency translated current signal.

Transconductance enhanced RF front-end

Embodiments of a frequency translated filter (FTF) are presented. An FTF includes a passive mixer and a baseband impedance. The baseband impedance includes a network of one or more passive components (e.g., resistors, inductors, and capacitors) that form a low-Q filter. The passive mixer is configured to translate the baseband impedance to a higher frequency. The translated baseband impedance forms a high-Q filter and is presented at the input of the FTF. The FTF can be fully integrated in CMOS IC technology (or others, e.g., Bipolar, BiCMOS, and SiGe) and applied in wireless receiver systems including GSM, Wideband Code Division Multiple Access (WCDMA), Bluetooth, and wireless LANs (e.g., IEEE 802.11).

Frequency translated filter

A method to provide a low-power clock signal or a low-noise clock signal is described herein. It is determined whether a low-power mode or a low-noise mode is in use. A voltage reference input of a low-dropout voltage regulator (LDO) is switched to a low-power voltage reference for low-power mode and to a low-noise voltage reference for low-noise mode. The LDO provides a constant voltage output to a crystal oscillator. A clock signal is generated using the crystal oscillator. The clock signal is limited using a low-power limiter to generate a low-power output clock signal and/or is limited using a low-noise limiter to generate a low-noise clock signal. The low-power output clock signal or the low-noise output clock signal is selected using a mux.

Configurable clock signal generator

A method for processing signals is disclosed and may include performing using one or more circuits in a multiband radio, functions including receiving an input signal from an oscillator that generates signals for each of a plurality of bands handled by the multiband radio. The received input signal may be divided. A feedback loop reference signal may be generated from the input signal. A coarse calibration signal and/or a fine calibration signal may be generated from the generated feedback loop reference signal. The oscillator may be calibrated utilizing the coarse calibration signal and/or the fine calibration signal. The input signal generated by the oscillator may be between about 3.4 GHz and 4 GHz. The receive input signal may be buffered. The generated feedback loop reference signal may also be buffered.

Method and system for a synthesizer/local oscillator generator (LOGEN) architecture for a quad-band GSM/GPRS radio

An electrostatic-discharge/impedance-matching circuit for use in radio frequency (RF) integrated circuits. The electrostatic-discharge/impedance-matching circuit comprises at least one shunt circuit operable to shunt current related to an over-voltage condition and at least one series element operably coupled to the shunt element. The shunt element and series element in combination provide electrostatic discharge protection for the RF signal processing circuit elements on the integrated circuit and also provide a matched input impedance for an incoming RF signal. Various alternate embodiments of the electrostatic-discharge/impedance-matching circuit include first and second shunt elements and a series element operably connected in combination to provide optimal electrostatic discharge protection and impedance matching. The electrostatic-discharge/impedance-matching circuit can be placed at various locations on the integrated circuit to provide optimal performance depending on the particular architecture of the integrated circuit.

Electrostatic protection circuit with impedance matching for radio frequency integrated circuits

Methods and systems for reducing parasitic capacitance of a buffer for an electric circuit are disclosed and may include coupling a gate of a first transistor to a first differential input of the buffer via a first capacitor, coupling a gate of a second transistor to a second differential input of the buffer via a second capacitor. The first and second transistors may be biased by a common mode output of a direct current (DC) voltage source for the buffer. The common mode output of the DC voltage source may be directly coupled to at least one differential output of the buffer via an inductor. The first transistor and the second transistor may comprise NMOS transistors and/or PMOS transistors. The DC voltage source may comprise a PMOS transistor and/or an NMOS transistor.

System and method for common mode bias for high frequency buffers

Methods and systems for processing signals for a multiband radio are disclosed herein. Aspects of the method may comprise dividing an input signal generated by an oscillator used to generate signals for each of a plurality of bands for the multiband radio. A feedback loop reference signal may be generated from the input signal and a coarse calibration signal may be generated from the feedback loop reference signal. The oscillator may be calibrated utilizing the coarse calibration signal. The input signal may be buffered and/or divided by a divide by four (4) divider circuit. The input signal generated by the oscillator may be between about 3.4 GHz and 4 GHz. The generated feedback loop reference signal may be buffered and/or divided prior to the calibration. The coarse calibration signal may comprise a 7-bit calibration signal. A fine calibration signal may be generated from the feedback loop reference signal.

A gain boost circuit and methodology are described for providing improved gain boosting with tuned amplifier circuits, such as differential low noise amplifier circuits having output resonant tank circuits. By selectively controlling the current source for a negative transconductance stage coupled between the differential amplifier output and the output resonant tank circuits, the amplifier gain may be adjusted to compensate for temperature variations. In addition, the amplifier gain boost may be selectively added, removed or even incrementally adjusted by using a current source control circuit in the negative transconductance stage to adjust the negative transconductance value generated by the negative transconductance stage.

Gain boosting for tuned differential LC circuits

A pulse on edge circuit includes a first pull up transistor having its gate terminal coupled to a delayed control signal and a second pull up transistor having its gate terminal coupled to an inverted delayed control signal. A first and second pull down transistors are coupled in series between the first pull up transistor and a low voltage bias, wherein the gates of the first and second pull down transistors are coupled to the delayed control signal and inverted control signal, respectively. A third and fourth pull down transistors are coupled in series between the second pull up transistor and the low voltage bias. The gates of the third and fourth pull down transistors are coupled to a control signal and the inverted delayed control signal, respectively.

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Huntington Beach, CA, United States of America

John Cumming Leete