Rambus Inc.

John Cronan Eble, Iii

John M Wilson

Lei Luo

Barry William Daly

Jared L Zerbe

Brian S Leibowitz

Wayne D Dettloff

Jade M Kizer

Jihong Ren

Teva J Stone

Hsuan-Jung Su

Frederick Abbott Ware

Kambiz Kaviani

Anthony Chan Carusone

Dustin Tarl Dunwell

Ian P Shaeffer

Scott C Best

John Wood Poulton

Carl William Werner

Kyung Suk Oh

Aliazam Abbasfar

Hanson Quan

WooPoung Kim

Technologies for converting quad data rates on a host interface to double data rates on a memory interface are described. One memory module includes a data buffer device with a host-side interface circuit that sends or receives first data to and from a host device at a quad data rate and a memory-side interface circuit that sends or receives second data to and from a set of memory devices at a first specified data rate that is less than the quad data rate. The memory module includes conversion circuitry to down-convert the first data at the quad data rate to the second data at the first specified data rate and up-convert the second data at the first specified data rate to the first data at the quad data rate.

Quad-data-rate (QDR) host interface in a memory system

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented 'fast turn-on' bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

Method and apparatus for source-synchronous signaling

Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

Integrated circuit having a multiplying injection-locked oscillator

A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.

Reference voltage generation and calibration for single-ended signaling

A camouflage circuit instantiated on a semiconductor substrate includes a transient-comparison circuit that briefly expresses a value representative of either a one or a zero in dependence upon reference elements that are visibly indistinct from a perspective normal to the planar surface substrate surface, but that nevertheless exhibit distinct electrical responses. Transient comparisons that define logic states only briefly vastly complicate the use of reverse-engineering tools and techniques that rely on optical stimulation to sense when transistors are on or off.

Methods and circuits for protecting integrated circuits from reverse engineering

A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.

Receiver resistor network for common-mode signaling

Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.

Asymmetric communication on shared links

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Chapel Hill, NC, United States of America

John Cronan Eble, Iii