International Business Machines Corporation

John Cocke

Peter W Markstein

George Radin

Jennifer Ceil Lai

Robert L Mercer

Marc Alan Auslander

Albert Y Chang

Mark F Mergen

Peter F Brown

Stephen A Della Pietra

Vincent J Della Pietra

Frederick Jelinek

Hsieh T Hao

Thomas H DiStefano

Robert K Montoye

Lalit R Bahl

Gary E Strait

Don Coppersmith

Brent Tzion Hailpern

Adrian Eric Seigler

Richard R Oehler

Joachim Hagenauer

Gregory F Grohoski

Richard LaVerne Malm

Vojin G Oklobdzija

Francis P Carrubba

Clifton D Cullum, Jr

John James Shedletsky

Norman H Kreitzer

Richard Fairbanks Arnold

Victoria I Markstein

A memory address translation and related control system for performing the dual functions of converting virtual memory addresses generated by the CPU into real memory addresses in a highly efficient and versatile manner and for controlling certain memory functions such as journalling. The address translation function comprises two steps, the first comprising converting the virtual address into a second virtual address or an effective address and finally the step of converting the effective address into a real memory address. The first step utilizes a set of special registers addressable by a small field to the CPU generated virtual address which converts the virtual address into an expanded form. The second or effective address is then used as the subject of the second or address translation step. To greatly enhance the translation of frequently used virtual addresses, a special set of translation tables referred to herein as a Translation Look-Aside, Buffer (TLB) contain current effective to real address translations for use where frequently referenced addresses are requested. The TLBs are addressed using a subset of the effective address whereupon the contents of the addressed TLB is examined for a match with the effective address. If the addresses match a successful address translation is possible and the real address stored in the address field of the TLB is available for system use. If the desired effective address is not present in the TLB, the page frame tables stored in main memory are accessed and searched for the desired effective address and if found the associated real address is accessed. Further a special data field is provided in both the TLBs and the page frame tables in main memory wherein a bit is provided for each line in the referenced page at a given effective to real address translation which bits may be used to indicate when a line of data has been accessed or altered.

Virtual memory address translation mechanism with controlled data persistence

The present invention is a system for translating text from a first source language into a second target language. The system assigns probabilities or scores to various target-language translations and then displays or makes otherwise available the highest scoring translations. The source text is first transduced into one or more intermediate structural representations. From these intermediate source structures a set of intermediate target-structure hypotheses is generated. These hypotheses are scored by two different models: a language model which assigns a probability or score to an intermediate target structure, and a translation model which assigns a probability or score to the event that an intermediate target structure is translated into an intermediate source structure. Scores from the translation model and language model are combined into a combined score for each intermediate target-structure hypothesis. Finally, a set of target-text hypotheses is produced by transducing the highest scoring target-structure hypotheses into portions of text in the target language. The system can either run in batch mode, in which case it translates source-language text into a target language without human assistance, or it can function as an aid to a human translator. When functioning as an aid to a human translator, the human may simply select from the various translation hypotheses provided by the system, or he may optionally provide hints or constraints on how to perform one or more of the stages of source transduction, hypothesis generation and target transduction.

System for parametric text to text language translation

Method and system for natural language translation

A floating point instruction control mechanism which processes loads and stores in parallel with arithmetic instructions. This results from register renaming, which removes output dependencies in the instruction control mechanism and allows computations aliased to the same register to proceed in parallel.

Instruction control mechanism for a computing system with register

A single floating point that produces the result A.times.B+C with A, B and C being floating point numbers. The operand C is shifted in parallel with the beginning phases of the multiplication. The result is produced after a single addition and normalization, reducing hardware, delay and rounding errors.

Floating point unit for calculating A=XY+Z having simultaneous multiply

A method and apparatus for controlling access to data blocks stored by addresses in a memory and concurrently accessible by a plurality of transactions is provided. The method includes the steps of receiving an address of a data block to be accessed by a first transaction, deriving from the address an access table entry corresponding to the data block where the entry includes lock data that governs access to the data block, and providing the access if permitted by the lock data, or providing the access, if not permitted by the lock data, and recording the occurrence of the access in the lock data.

Memory controller for protected memory with automatic access granting

A procedure for use in an optimizing compiler termed 'reassociation' determines the preferred order of combining terms in a sum so as to produce loop invariant subcomputations, or to promote common subexpressions among several essential computations, by applying the associative law of addition. To achieve this, the requisite optimization of an object program or program segment, the following discrete steps must be performed after the strongly connected regions, USE and DEF chains have all been identified:

Method for improving the efficiency of arithmetic code generation in an

Hierarchical memory system including separate cache memories for storing

A plurality of intelligent work stations are provided access to a shared memory through a switching hierarchy including a first array of mapping boxes for receiving a first address from an intelligent work station and including a virtual address and offset and for converting the virtual address into a terminal switch port designation and logical address, a first switch for forwarding the logical address and offset to the designated terminal switch port, a second array of mapping boxes for receiving the logical address and offset and for converting the logical address into a memory switch port designation and physical address, and a second switch for forwarding the physical address and offset to the designated memory switch port as an address to the shared memory.

Interconnect scheme for shared memory local networks

A method for use during the optimizatin phase of an optimizing compiler for performing global common subexpression elimination and code motion which comprises: Determining the code `basis` for the object program which includes examining each basic block of code and determining the `basis` items on which each computation depends wherein `basis` items are defined as operands which are referenced in a basic block before being computed. The method next determines the 'kill set' for each `basis` item. Following this UEX, DEX, and THRU are determined for each basic block using the previously determined `basis` and 'kill set' information. AVAIL and INSERT are computed from UEX, DEX, and THRU, and appropriate code insertions are made at those locations indicated by the preceding step, and finally redundant code is removed using the AVAIL set.

Method for improving global common subexpression elimination and code

A method operable within an optimizing compiler to move certain range check instructions out of single entry strongly connected regions or loops and into linear regions of the instruction stream whereby computational efficiency is increased with no loss of program accuracy. The method comprises placing a range check trap instruction into the header node of the SCR provided there is only one conditional exit from the SCR, modifying the conditional exit test based on the value of the induction variable v, and inserting a new check at the loop exit point(s) to insure that the induction variable has reached the value it would have obtained in the original (unmodified) program.

Optimization of range checking

Virtual memory address translation mechanism with controlled data

A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency. Still more particularly, the condition register architecture provides for the efficient handling of multiply and divide operations and provides for the more efficient execution of certain decimal operations within such a reduced instruction set host computer system.

Condition register architecture for a primitive instruction set machine

A mechanism for performing a run-time storage address validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its function in one machine cycle in the event that a trap exception does not cause an interrupt. In the rare instance when an interrupt is necessary, a number of machine cycles will be impacted. The mechanism comprises a minimum amount of logic circuitry for determining the trap condition operating in conjunction with conventional, previously existing compare, branch instruction testing, and interrupt generation circuitry.

Mechanism for implementing one machine cycle executable trap

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Bedford, NY, United States of America

John Cocke