International Business Machines Corporation

Ftl Systems, Inc.

Other

John Christopher Willis

David Arnold Luick

Russell Dean Hoover

Frederick Jacob Ziegler

Robert Neill Newshutz

Donald Francis Baldus

George Wayne Nation

Philip Braun Winterfield

William A Hammond, Jr

Nancy Joan Duffield

Mayan Moudgill

Steven Lee Gregor

Ronald Edward Fuhs

Lishing Liu

Steven Lyn Rogers

Philip A Wilsey

Kenneth J Kiefer

Ruth A Betcher

Robert W Burton

David Robert Engebretsen

A light symbol projection device is disclosed. The light symbol projection device has a housing which is temporarily secured within a receiving mechanism. The receiving mechanism is embedded within a product such as, for example, a shoe. The light symbol housing may project, in various colors, a word, pattern, symbol, logo or other indicia on the ground. The light symbol housing may be interchangeable so that the receiving mechanism may receive various light symbol housings having different light projections. In one embodiment, a speaker associated with the device may also provide an audible sound.

Light symbol projection device

An innovative realization of computer hardware, software and firmware comprising a multiprocessor system wherein at least one processor can be configured to have a fixed instruction set and one or more processors can be statically or dynamically configured to implement a plurality of processor states in a plurality of technologies. The processor states may be instructions sets for the processors. The technologies may include programmable logic arrays.

Multiprocessor computer system and method having at least one processor with a dynamically reconfigurable instruction set

An apparatus is disclosed for the optical generation of clock signals with tunable frequency and low jitter. A laser source serves as both the carrier used to transmit the clock signal for use by other optical, electronic or hybrid circuit elements and the original modulation time base. A fraction of the original laser source undergoes one or more stages of frequency division before being recombined as a modulation signal with the remaining laser beam. Transmission of the resulting signal via single mode fiber and dividers retains the low jitter properties of the modulated signal. By starting with a clock signal of optical frequency then dividing downward in frequency, comparatively high frequency clocks may be generated, notably in the GigaHertz and TeraHertz frequency ranges.

Highly tunable, low jitter optical clock generation

A hardware/software design tool converts an electronic design specification and zero or more technology specifications into realization of the electronic design in computer hardware, software and firmware. It compiles design and logic technology specifications into a model which can be utilized for behavioral analysis of logical characteristics. It translates partitions of the design and one or more logic technologies into one or more processor intermediates or binaries suitable for execution on multi-purpose processing units. It translates partitions of the design and logic technology into a collection of cells and interconnects suitable for input to physical design processes such as is required to target a FPGA, ASIC, system-on-a-chip or custom logic. It analyzes behavior of the embedded binaries running on processing units and implementations augmented by additional physical technology and parameters, yielding a more detailed prediction of the resulting hardware/software system behavior when realized through manufacturing.

Method for generating compiler, simulation, synthesis and test suite from a common processor specification

An innovative method is taught for accelerating the simulation rate of differential equation systems having behavior piece-wise continuous in both value and time. Specifically, a system of differential equations representing the behavior of a physical system comprised of electronic, optical, or mechanical components may be simulated more rapidly using this method. The method utilizes incremental and iterative reconfiguration of digital logic wherein each configuration of the logic operates to yield a unique future value or range of values for each time-varying state variable within a system of equations representing a linear approximation of the original differential equation system for state variable values defined initially or at the onset of an iteration. Various configurations of the digital logic may be pre-computed or computed on demand, optionally caching such configurations for subsequent reuse.

Accelerating simulation of differential equation systems having continuous behavior

A method is taught for increasing the steady-state verification speed of analog and mixed signal design through increased simulation speed, model abstraction by probing an existing component model or actual device and formal comparison of distinct component models. The innovative method taught here incrementally generates processor instructions optimized for operating the analog solver around a specific set of values (the operating context), caches sequences and applies the currently applicable operating context at each point in the simulation. The invention discloses a method for semi-automatically generating a mixed-signal or analog model based on iterative probing of an existing device or behavioral simulation. The invention teaches a method for model abstraction to alter the level of detail present in a running simulation. A means for graphically evaluating the match quality constitutes the final innovative step. The innovative method for the formal comparison of two analog or mixed signal models within a prescribed operating range for each interface between the model and its environment without the need for exhaustive simulation.

Semi-automatic generation of behavior models continuous value using iterative probing of a device or existing component model

A hardware/software design tool converts an electronic design specification and zero or more technology specifications into realization of the electronic design in computer hardware, software and firmware. It compiles design and logic technology specifications into a model which can be utilized for behavioral analysis of logical characteristics. It translates partitions of the design and one or more logic technologies into one or more processor intermediates or binaries suitable for execution on multi-purpose processing units. It translates partitions of the design and logic technology into a collection of cells and interconnects suitable for input to physical design processes such as is required to target, a FPGA, system-on-a-chip or custom logic. It analyzes behavior of the embedded binaries running on processing units and implementations augmented by additional physical technology and parameters, yielding a more detailed prediction of the resulting hardware/software system behavior when realized through manufacturing.

Hardware/software design tool and language specification mechanism enabling efficient technology retargeting and optimization

An apparatus and method for semi-automated generation and application of language conformity tests is disclosed. Generation is based on interpretative or compiled processing of a generator-oriented, formal language specification embodying lexical, syntactic and semantics aspects of a language standard as well as specific test strategies. Such test strategies control the order and extent of the test sequence generated and applied. Both test case generation and application of test cases may occur in parallel.

Apparatus and method for semi-automated generation and application of language conformity tests

An apparatus and method for performing multithreaded operations includes partitioning the general purpose and/or floating point processor registers into register subsets, including overlapping register subsets, allocating the register subsets to the threads, and managing the register subsets during thread switching. Register overwrite buffers preserve thread resources in overlapping registers during the thread switching process. Thread resources are loaded into the corresponding register subsets or, when overlapping register subsets are employed, into either the corresponding register subset or the corresponding register overwrite buffer. A thread status register is utilized by a thread controller to keep track of READY/NOT-READY threads, the active thread, and whether single-thread or multithread operations are permitted. Furthermore, the registers in the register subsets include a thread identifier field to identify the corresponding thread. Register masks may also be used to identify which registers belong to the various register subsets.

Apparatus and method for retrofitting multi-threaded operations on a computer by partitioning and overlapping registers

In a computer system and a processor which has the capability to do multithreaded processor, the computer system and processor use idle register/storage functional units within the processor core to transfer the state of a thread out of the processor to memory or from memory to the processor core. The register/storage functional units are interrogated dynamically so that this transfer occurs only when the register/storage functional units are idle and not being used for normal instructions. Thus, a state may be transferred in whole if there are many cycles when the register/storage functional unit is idle or it may be transferred in part if there an insufficient number of no-op instructions for the entire state. A context switch unit in the processor then has appropriate registers and logic control to keep track of the state of the thread that is being &ldquo;idly&rdquo; transferred and then transfer the remaining registers when a register/storage functional is available or &ldquo;idle.&rdquo;

Moving data in and out of processor units using idle register/storage functional units

A method and system for providing cache coherence despite unordered interconnect transport. In a computer system of multiple memory devices or memory units having shared memory and an interconnect characterized by unordered transport, the method comprises sending a request packet over the interconnect from a first memory device to a second memory device requiring that an action be carried out on shared memory held by the second memory device. If the second memory device determines that the shared memory is in a transient state, the second memory device returns the request packet to the first memory device; otherwise, the request is carried out by the second memory device. The first memory device will continue to resend the request packet each time that the request packet is returned.

Method and system for maintaining cache coherence in a

A method and apparatus for maintaining coherence between shared data stored within a plurality of memory devices, each memory device residing in a different node within a tightly coupled multiprocessor system. Each node includes a 'local coherence unit' and an associated processor. A cache unit is associated with each memory/processor pair. Each local coherence unit maintains a table which indicates whether the most current copy of data stored within the node resides in the local memory, in the local cache, or in a non-local cache. The present invention includes a 'global coherence' unit coupled to each node via the logical interconnect. The global coherence unit includes a interconnect monitoring device and a global coherence table. When data which resides within the memory of a first node is transferred to a second node, the interconnect monitoring device updates the global coherence table to indicate that the data is being shared. The global coherence table also preferably indicates in which node a copy of the most current data resides.

Multiprocessor cache coherence directed by combined local and global

A distributed, compiler-oriented database is disclosed with operating modes including parallel compilation, parallel simulation and parallel execution of computer programs and hardware models. The invention utilizes a hardware apparatus consisting of shared memory multiprocessors, optionally augmented by processors with re-configurable logic execution pipelines or independently scheduled re-configurable logic blocks and a software database apparatus, manifest in the hardware apparatus, in order to efficiently support parallel database clients such as a source code analyzer, an elaborator, an optimizer, mapping and scheduling, code generation, linking/loading, execution/simulation, debugging, profiling, user interface and a file interface.

Compiler-oriented apparatus for parallel compilation, simulation and

Compile and/or run time instruction scheduling is used in a multiprocessing system to reorder memory access instructions such that a strongly consistent programming model is emulated in a fashion transparent to the programmer. The multiprocessing system detects potential shared memory conflicts, avoiding these conflicts by restarting operation of the affected processing unit at a predetermined previous state, previously archived in a rollback register set, and resuming instruction execution from that state.

Reordering of memory reference operations and conflict resolution via

A processor includes an alias unit having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries that consist of a base address in the processor memory to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor can optionally include a data cache and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.

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Rochester, MN, United States of America

John Christopher Willis