Micron Technology Incorporated

John Christopher M Sancon

Karthik Sarpatwari

Nevil N Gajera

Lingming Yang

Seth A Eichmeyer

Dmitry A Vengertsev

Nicola Ciocchini

Jing Gong

Tom Tangelder

Apparatuses and methods can be related to implementing a binary neural network in memory. A binary neural network can be implemented utilizing a resistive memory array. The memory array can comprise programmable memory cells that can be programed and used to store weights of the binary neural network and perform operations consistent with the binary neural network. The weights of the binary neural network can correspond to non-zero values.

Binary neural network in memory

Systems, apparatuses, and methods related to a row hammer refresh operation are described herein. An example apparatus can include an array of memory cells of a memory device. The array of memory cells can include a plurality of dies and at least one of the plurality of dies is a row hammer die. The example apparatus can include a memory controller coupled to the array of memory cells. The memory controller can perform a number of operations on the array of memory cells. The memory controller can detect a quantity of accesses associated with the row hammer die and based on the number of operations performed. The memory controller can, in response to detection of a threshold quantity of accesses of a group of memory cells in the row hammer die, perform a refresh operation on a group of memory cells in an additional die of the plurality of dies.

Row hammer refresh operation

Systems, methods, and apparatus related to memory devices. In one approach, a memory device includes a sense amplifier, a counter, and memory having memory cells. Access lines are used to select the memory cells for performing write operations. The memory device includes a controller to control the applying of a voltage to the memory cell. The voltage is applied during a write operation using the access lines. The sense amplifier is used to determine whether the memory cell reaches a threshold state or snaps. In response to determining that the memory cell does not snap, a write error count is incremented using the counter. The controller reads the counter to determine the write error count, and based on the write error count, the controller performs one or more media management or memory device control actions.

Write error counter for media management in a memory device

The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. An embodiment includes a memory having a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells, and circuitry configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.

Performing refresh operations on memory cells

Methods and systems include memory devices having multiple memory cells configured to store data. The memory devices also include control circuitry including retry circuitry. The retry circuitry is configured to receive a read command having a target address. The retry circuitry is also configured to determine that the target address of the data stored in the memory cells is to be reused from a previous read operation. Additionally, the retry circuitry is configured to cause reading of the data from a sense amplifier latch from the previous read operation by reusing the target address. Specifically, reusing the target address includes bypassing rereading the data into the sense amplifier latch from the memory cells for a current read operation.

Reset read disturb mitigation

The present disclosure includes apparatuses, methods, and systems for performing refresh operations on memory cells. A memory can include a group of memory cells and one or more additional memory cells whose data state is indicative of whether to refresh the group of memory cells. Circuitry is configured to apply a first voltage pulse to the group of memory cells to sense a data state of the memory cells of the group, apply, while the first voltage pulse is applied to the group of memory cells, a second voltage pulse having a greater magnitude than the first voltage pulse to the one or more additional memory cells to sense a data state of the one or more additional memory cells, and determine whether to perform a refresh operation on the group of memory cells based on the sensed data state of the one or more additional memory cells.

Growing community of inventors

Boise, ID, United States of America

John Christopher M Sancon