Agere Systems Inc.

Lsi Corporation

Other

At&t Bell Laboratories

Agere Systems Guardian Corp.

Agere Syatems Inc.

John Christopher Kriz

Dipankar Bhattacharya

Makeshwar Kothandaraman

Bernard Lee Morris

Yehuda Smooha

Pankaj Kumar

Pramod Elamannu Parameswaran

Jeffrey Jay Nagy

Vani Deshpande

Stefan Allen Siegel

Duane J Loeper

Joseph E Simko

Antonio M Marques

Carol Ann Huber

Peter J Nicholas

Ashish V Shukla

William Burdett Wilson

Paul K Hartley

Eric D Persson

Samuel Khoo

Gregg R Harleman

Che Coi Leung

Brian C Lacey

James John Bradley

Juergen Pianka

Mean-sea Tsay

Dharmeshkumar N Bhakta

Punkaj Kumar

A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions.

Hybrid impedance compensation in a buffer circuit

A voltage translator circuit () includes an input stage () adapted for receiving an input signal referenced to a first voltage supply (VDD core), a latch () adapted for connection to a second voltage supply (VDD) and operative to at least temporarily store a logic state of the input signal, and a voltage clamp () coupled between the input stage () and the latch (). The voltage clamp () is operative to set a maximum voltage across the latch () to a first prescribed level and to set a maximum voltage across the input stage to a second prescribed level. The voltage translator circuit () generates a first output signal (II) at a junction between the latch () and the voltage clamp (). The voltage translator circuit generates a second output signal () at a junction between the voltage clamp () and the input stage ().

Voltage level translator circuit

A differential buffer circuit having increased output voltage swing includes a differential input stage including at least first and second transistors, the first and second transistors being operative to receive first and second signals, respectively. The buffer circuit further includes a bias stage connected between the differential input stage and a first voltage source. The bias stage is operative to generate a quiescent current as a function of a third signal supplied to the bias stage. A load circuit is connected between a second voltage source and the differential input stage, first and second differential outputs of the buffer circuit being generated at a junction between the load circuit and the differential input stage. The load circuit includes first and second switching elements coupled with the first and second transistors, respectively. The first switching element is operative to electrically connect the first differential output to the second voltage source when the first transistor is turned off. The second switching element is operative to electrically connect the second differential output to the second voltage source when the second transistor is turned off.

Current-mode logic buffer with enhanced output swing

A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.

Mode latching buffer circuit

A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit having a pull-up portion comprising at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage in the buffer circuit and is operative to generate a first control signal indicating a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage over variations in PVT conditions to which the buffer circuit may be subjected. The compensation circuit further includes a control circuit generating first and second sets of digital control bits for compensating the pull-up and pull-down portions in the output stage over prescribed variations in PVT conditions. The second set of digital control bits is generated based at least on the first set of digital control bits and the first control signal.

Impedance compensation in a buffer circuit

A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of an IO receiver, and controllably generating a second bias voltage from an external voltage supplied through an IO pad to be within the upper tolerable limit of the operating voltage of the IO receiver. The method also includes deriving an output voltage from the first bias voltage during a normal condition and a tolerant condition, and deriving the output voltage from the second bias voltage during a failsafe condition. The tolerant condition is a mode of operation where the external voltage supplied through the IO pad varies from zero to a value higher than the supply voltage, and the failsafe condition is a mode of operation where the supply voltage is zero.

Interfacing between differing voltage level requirements in an integrated circuit system

A method includes controllably generating a first bias voltage from a supply voltage to be within an upper tolerable limit of an operating voltage of one or more constituent active circuit element(s) of an Input/Output (IO) core device of an integrated circuit (IC) to be interfaced with an IO pad, and controllably generating a second bias voltage from an external voltage supplied through the IO pad to be within the upper tolerable limit of the operating voltage of the one or more constituent active circuit element(s) of the IO core device to be interfaced with the IO pad. The method also includes controllably utilizing a control signal generated by the IO core to derive an output bias voltage from the first bias voltage during a driver mode of operation or the second bias voltage during a failsafe mode of operation and a tolerant mode of operation.

Bias voltage generation to protect input/output (IO) circuits during a failsafe operation and a tolerant operation

An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.

Electrostatic discharge protection circuit

Described embodiments provide for protecting from DC and transient over-voltage conditions an input/output ('I/O') buffer having first and second I/O transistors. The first I/O transistor is coupled to a first over-voltage protection circuit adapted to prevent an over-voltage condition on at least the first I/O transistor. The second I/O transistor is coupled to a second over-voltage protection circuit adapted to prevent an over-voltage condition on at least the second I/O transistor. First and second bias voltages are generated from an operating voltage of the buffer. A third bias voltage is generated from either i) the first bias voltage, or ii) an output signal voltage of the buffer and a fourth bias voltage is generated from either i) the second bias voltage, or ii) the output signal voltage of the buffer. The third and fourth bias voltages are provided to the first and second over-voltage protection circuits, respectively.

I/O buffer with low voltage semiconductor devices

Disclosed is a bias circuit with a first resistor connected between the supply voltage and a feedback node. Resistors are connected in series between the feedback node and the reference supply voltage. The connections between the resistors define at least one bias voltage. A second resistor is connected between the feedback node and a first drain node. A first field-effect transistor has a first gate node, the first drain node, and a first source node. The gate node is connected to the first supply voltage. A second field-effect transistor has a second gate node, a second drain node, and a second source node. The second drain node is connected to the first source node. The second gate node is connected to the bias voltage. The second source node is connected to an output signal node. The output signal node capable of experiencing an overshoot voltage.

Bias circuit scheme for improved reliability in high voltage supply with low voltage device

A circuit includes a first comparator block configured to output a voltage equal to a higher of a supply voltage and a bias voltage, a second comparator block configured to output a voltage equal to a higher of the bias voltage and an external voltage supplied through an Input/Output (IO) pad, and a third comparator block configured to output a voltage equal to a higher of the output of the first comparator block and the output of the second comparator block. A voltage across one or more constituent active element(s) of each of the first comparator block, the second comparator block, and the third comparator block is within an upper tolerable limit thereof during each of a normal operation, a failsafe operation, and a tolerant operation.

Floating well circuit operable in a failsafe condition and a tolerant condition

In memory circuitry, to ensure that a memory device, such as a DDR3 RDIMM, safely operates in self-refresh mode while the memory controller is powered down and off, the memory device's clock enable (CKE) input is connected to both (i) the CKE signal applied by the memory controller and (ii) a termination voltage provided by the power module. To power down the memory controller, the memory controller drives the CKE signal low, then the power module drives the termination voltage low, then the power module powers down the memory controller. To resume normal operations, the power module powers up the memory controller, then the memory controller drives the CKE signal low, then the power module powers up the termination voltage. By holding the termination voltage low, the memory circuitry ensures that the memory device stays in self-refresh mode while the memory device is powered down and off.

Memory device control for self-refresh mode

A compensated buffer circuit operative in one of at least a first mode and a second mode includes a plurality of output blocks and a plurality of predrivers, each of the predrivers having an output connected to an input of a corresponding one of the output blocks. Respective outputs of the output blocks are connected together and form an output of the buffer circuit. The output blocks are arranged in a sequence and are binary weighted such that a drive strength of a given one of the output blocks is about twice as large as a drive strength of an output block immediately preceding the given output block. Each of the predrivers selectively enables the corresponding output block connected thereto as a function of a control signal supplied to the predriver for compensating the buffer circuit for PVT variations to which the buffer circuit may be subjected. The respective control signals supplied to the predrivers collectively represent a binary code word, the binary code word in the second mode being equivalent to an arithmetic shift of the binary code word in the first mode.

Multiple-mode compensated buffer circuit

A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal. The processor is operative to control the value of the second current so that the second current is substantially equal to the first current.

Enhanced output impedance compensation

A circuit for selectively bypassing a capacitive element includes at least one NMOS device selectively connectable across the capacitive element to be bypassed, and at least first and second PMOS devices. The PMOS devices are selectively connectable together in series across the capacitive element to be bypassed. The NMOS device provides a first bypass path and the first and second PMOS devices collectively provide a second bypass path.

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Palmerton, PA, United States of America

John Christopher Kriz