International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Advanced Micro Devices Corporation

Globalfoundries Inc.

Adeia Semiconductor Solutions LLC

John Christopher Arnold

Ashim Dutta

Sean David Burns

Dominik Metzler

Yunpeng Yin

Chi-Chun Liu

Daniel C Edelstein

Ekmini Anuja De Silva

Nelson M Felix

Chih-Chao Yang

Muthumanickam Sankarapandian

Theodorus E Standaert

Matthew Earl Colburn

Yann Mignot

Yongan Xu

Steven J Holmes

Michael Rizzolo

Sivananda K Kanakasabapathy

Sampath Purushothaman

Terry Allen Spooner

Stefan Schmitz

Sagarika Mukesh

David V Horak

Hosadurga K Shobha

Stuart A Sieg

Yann A M Mignot

Somnath Ghosh

Timothy Mathew Philip

Ruilong Xie

Robert Dennis Miller

Alfred Grill

Takeshi Nogami

Elbert Emin Huang

Griselda Bonilla

Dario Leonardo Goldfarb

Donald Francis Canaperi

Willi Volksen

Cornelius Brown Peethala

Kuan-Neng Chen

William J Cote

Rangarajan Jagannathan

Satya Venkata Nitta

Geraud J Dubois

Kisup Chung

E Todd Ryan

Xuefeng Hua

Devendra K Sadana

Bruce Bennett Doris

Lawrence Alfred Clevenger

Brent A Anderson

Tenko Yamashita

Carl John Radens

Stephen W Bedell

Louis L Hsu

Keith E Fogel

Oleg Gluschenkov

Vijay Narayanan

Dechao Guo

Dureseti Chidambarrao

Balasubramanian Pranatharthiharan

Son Van Nguyen

Keith Kwong Hon Wong

Timothy Joseph Dalton

Michael Patrick Chudzik

Jon Michael Slaughter

Richard Stephan Wise

Shreesh Narasimha

Kisik Choi

Huiming Bu

Tze-Chiang Chen

Hiroyuki Miyazoe

Albert Manhee Chu

Vamsi Krishna Paruchuri

Daniel Sanders

Pushkara Rao Varanasi

Barry P Linder

Nathan P Marchack

Michael C Gaidis

Robert L Bruce

Stefan Harrer

Alessandro Cesare Callegari

Raghuveer Reddy Patlolla

Sebastian Ulrich Engelmann

Kuang-Jung Chen

Albert M Young

Allen H Gabor

Karen Elizabeth Petrillo

Jeffrey C Shearer

Ying Li

Siddhartha Panda

Rajeev Malik

Balasubramanian S Pranatharthi Haran

Michael Abramovich Gribelyuk

Michelle Leigh Steen

Catherine B Labelle

Kai Zhao

Prasad Bhosale

Alan C Thomas

Glenn A Biery

Brian L Tessier

Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

Selective gas etching for self-aligned pattern transfer

A semiconductor structure includes logic device and passive device regions. The logic device region includes field effect transistors (FETs) having a gate structure and a source/drain region disposed on opposing sides of the gate structure. At least one source/drain region extends within a buried dielectric layer for electrically connecting a FET to a backside power rail (BPR). The passive device region includes passive devices disposed on a first side of a first semiconductor layer. A second semiconductor layer is disposed above a second side of the first semiconductor layer opposing the first side. A backside interlevel dielectric (BILD) is above the second semiconductor layer and the buried dielectric layer. The BPR is embedded within the BILD in the logic device region. A top surface of the BILD in the passive device region is coplanar with a top surface of the BPR and the BILD in the logic device region.

Semiconductor passive device integration for silicon-on-insulator substrate

A novel bevel etch sequence for embedded metal contamination removal from BEOL wafers is provided. In one aspect, a method of processing a wafer includes: performing a bevel dry etch to break up layers of contaminants with embedded metals which, post back-end-of line metallization, are deposited on a bevel of the wafer, which forms a damaged layer on surfaces of the wafer, and then performing a sequence of wet etches, following the bevel dry etch, to render the bevel of the wafer substantially free of contaminants, wherein the sequence of wet etches includes etching the damaged layer to undercut and lift-off any remaining contaminants. A wafer, processed in this manner, having a bevel that is substantially free of contaminants is also provided.

Embedded metal contamination removal from BEOL wafers

A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

Backside power rails and power distribution network for density scaling

Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.

Selective patterning of vias with hardmasks

A method of making a back-end-of-line (BEOL) component includes filling spaces in a layer of metal material and a layer of hardmask material with a layer of scaffolding material. The method further includes forming at least one plug on top of the layer of metal material such that the at least one plug is integrally formed with the layer of scaffolding material. The method further includes removing the layer of hardmask material such that a top surface of the layer of metal material is exposed except where the at least one plug is formed on top of the layer of metal material. The method further includes recessing the layer of metal material where the top surface of the layer of metal material is exposed. The method further includes removing the scaffolding material.

Subtractive patterning of interconnect structures

Embodiments of the present invention are directed to fabrication method and resulting structures for placing self-aligned top vias at line ends of an interconnect structure. In a non-limiting embodiment of the invention, a line feature is formed in a metallization layer of an interconnect structure. The line feature can include a line hard mask. A trench is formed in the line feature to expose line ends of the line feature. The trench is filled with a host material and a growth inhibitor is formed over a first line end of the line feature. A via mask is formed over a second line end of the line feature. The via mask can be selectively grown on an exposed surface of the host material. Portions of the line feature that are not covered by the via mask are recessed to define a self-aligned top via at the second line end.

Placing top vias at line ends by selective growth of via mask from line cut dielectric

A method of manufacturing a semiconductor device is provided. The method includes forming a plurality of metal lines on substrate, forming a sacrificial dielectric material layer between the metal lines, forming a hardmask over at least one of the metal lines, etching at least one of the metal lines that is not covered by the hardmask, treating the sacrificial dielectric material layer to soften the layer. The method also includes removing the treated sacrificial dielectric material layer.

Spin on scaffold film for forming topvia

A semiconductor device structure includes a metallization stack that has one or more patterned metal layers in a logic area and a memory area. At least one memory device is disposed above the metallization stack. A first level logic metal layer is coupled to a patterned metal layer of the one or more patterned metal layers in the logic area. A first level memory metal layer is formed above the first level logic metal layer and is coupled to a top electrode of the memory device stack. A distance between the one or more patterned metal layers in the logic area and the first level logic metal layer is smaller than the distance between the one or more patterned metal layers in the memory area and the first level memory metal layer.

Embedding magneto-resistive random-access memory devices between metal levels

A method for fabricating a semiconductor device includes recessing a first odd hardmask and a first even hardmask to form recessed odd and even hardmasks, forming a first conductive hardmask including first conductive hardmask material on the recessed odd hardmask and a second conductive hardmask on the recessed even hardmask, and forming self-aligned vias at line ends corresponding to the first odd and even conductive lines based at least in part on the first and second conductive hardmasks.

Method for fabricating a semiconductor device including self-aligned top via formation at line ends

A method for fabricating a semiconductor device includes forming a plurality of mandrel cuts from a first set of mandrels of a base structure using lithography, surrounding the first set of mandrels and a second set of mandrels of the base structure with spacer material to form mandrel-spacer structures, forming a flowable material layer on exposed surfaces of the mandrel-spacer structures, and performing additional processing, including forming a plurality of dielectric trenches within the base structure based on patterns formed in the flowable material layer.

Litho-etch-litho-etch with self-aligned blocks

A method of forming a semiconductor structure includes forming a memorization layer over a substrate, forming a first self-aligned double patterning (SADP) stack including a first organic planarization layer (OPL), masking layer, set of mandrels, and set of spacers, and forming a patterned memorization layer by transferring a first pattern of the first set of spacers to the memorization layer. The method also includes forming a second SADP stack comprising a second OPL, masking layer, set of mandrels, and set of spacers, and forming an array of pillars by transferring a second pattern of the second set of spacers to the patterned memorization layer. The first and second OPL and the first and second sets of mandrels are a spin-on coated OPL material, and the memorization layer and first and second masking layers are a material configured for removal selective to the spin-on coated OPL material.

Back-end-of-line compatible processing for forming an array of pillars

Methods for forming an integrated circuit are provided. Aspects include providing a wafer substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure, the memory area interconnect structure comprising metal interconnects formed within a first interlayer dielectric, recessing a portion of the memory area interconnect structure, forming a bottom electrode contact on the recessed portion of the memory area interconnect structure, forming a bottom electrode over the bottom electrode contact, forming a protective dielectric layer over the non-memory area interconnect structure, and forming memory element stack layers on a portion of the bottom electrode.

Embedded MRAM device formation with self-aligned dielectric cap

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North Chatham, NY, United States of America

John Christopher Arnold