Seagate Technology Incorporated

Seagate Technologies, Inc.

John Chester Masiewicz

Sean R Atsatt

Jeffrey Alan Miller

Marvin Mang-Yin Lum

John Marc Wright

Pervez Edul Virjee

In a computer data storage system configured for patching Read Only Memory (ROM) by remapping data sections, the ROM containing a token to define the start of each one of the data sections and a patch existing for at least one of the data sections, the patch providing additional data at the start of the data section; whereby the patch is included in one of the data sections when an access to one of the data sections is initiated at the token. The patch further optionally replaces at least a part of one of the data sections. The patch may be in writeable memory and if so, the ROM appears writeable thereby. The indicator will normally be a software No Operation or non-destructive instructive, since a No Operation instruction (NOP) causes a one cycle pause in the processor and allows time for the patch to be smoothly integrated.

Method and apparatus for remapping read only memory locations

An ATA-compatible drive interface with error correction and detection capabilities is disclosed. Being fully ATA backward compatible, this interface functions with the same physical cable and connectors as current ATA systems, employs bus drivers that are the same as or backward compatible with those provided by earlier versions of the ATA standard and uses signals with cable signal transitions no faster than those presently seen by current ATA devices. The error detection feature indicates when a data block is erroneously transferred between the device and host; the error correction feature identifies the words transmitted in error and corrects those words on the receiving side of the interface. So that ATA backward compatibility is maintained, the data integrity checking feature does not require additional words in a data transfer, and the data correction feature does not require new data transfer protocols or additional data transfer overhead. Also disclosed are interface circuitry and a new ATA-compatible transfer mode capable of transferring data at 40 MB/sec, the rate supported by local bus adapters for disk drives. Given the physical limits of the ATA cables and connectors, the error correction and detection features are especially useful for correcting data words corrupted during high-speed transmission; however, error correction and detection can also operate independently of the fast transfer mode. Consistent with full backward compatibility, a hard drive configured with the new, fast, error-correcting interface is transparently functional when plugged into a current ATA adapter provided by a legacy computer system.

Fast ATA-compatible drive interface with error detection and/or error correction

An ATA-compatible drive interface with error correction and detection capabilities is disclosed. Being fully ATA backward compatible, this interface functions with the same physical cable and connectors as current ATA systems, employs bus drivers that are the same as or backward compatible with those provided by earlier versions of the ATA standard and uses signals with cable signal transitions no faster than those presently seen by current ATA devices. The error detection feature indicates when a data block is erroneously transferred between the device and host; the error correction feature identifies the words transmitted in error and corrects those words on the receiving side of the interface. So that ATA backward compatibility is maintained, the data integrity checking feature does not require additional words in a data transfer, and the data correction feature does not require new data transfer protocols or additional data transfer overhead. Also disclosed are interface circuitry and a new ATA-compatible transfer mode capable of transferring data at 40 MB/sec, the rate supported by local bus adapters for disk drives. Given the physical limits of the ATA cables and connectors, the error correction and detection features are especially useful for correcting data words corrupted during high-speed transmission; however, error correction and detection can also operate independently of the fast transfer mode. Consistent with full backward compatibility, a hard drive configured with the new, fast, error correcting interface is transparently functional when plugged into a current ATA adapter provided by a legacy computer system.

Fast AtA-compatible drive interface with error detection and/or error

Translating between physical and logical (or virtual) address spaces occurs autonomously using information decoded by an address mode translator from command bits within a host CPU issued command. The translator communicates with a hard disc controller unit local microprocessor or microcontroller and controller unit task registers. A host CPU issued command interrupts the local microprocessor and activates the address mode translator by writing to an appropriate controller unit task register using indirect addressing. The address mode translator preferably provides four algorithms, with algorithm selection occurring autonomously according to the decoded command bits. The algorithms provide physical block address to physical CHS cylinder-head-sector conversion, logical CHS to logical block address conversion, and also provide divide and multiply functions, useful for disc caching. Upon completion of the conversion or other function procedure, the address translator signals that the processed result is ready for reading by the controller unit local microprocessor or microcontroller. The translator may be implemented as a microprogrammed sequencer with an instruction set tailored to perform linear address translations and stored in memory associated with the local microprocessor. Alternatively, the instruction set may be downloaded by the microprocessor from disc drive software. The address translator provides the microprocessor with a translated address in a usable form more rapidly than if the local microprocessor had made the translation.

Autonomous high speed linear space address mode translation for use with

A mechanism determines at least an approximation of output load coupled to a programmable output buffer, and then programs the buffer to source/sink an amount of output current appropriate to the load to be driven. The mechanism includes a load recognition unit, an optional signal conditioner, and a reconfiguration logic module. In interface-governed applications, the load recognition unit senses an interface bit (AT Attachment interface), or causes the output buffer to act as a master unit that polls the interface connection to determine the number of attached loads (SCSI interface). The recognition unit then outputs a signal that may be conditioned before being input to a reconfiguration logic module that outputs appropriate control signals that program the buffer. Alternatively, the load recognition unit may measure the shunt capacitance associated with the load by using a reference current source and an analog/digital converter. The resultant voltage developed across the shunt capacitance provides a measure of the load impedance, which is used by the reconfiguration logic module to output control signals appropriately configuring the output buffer. Preferably the output buffer includes a plurality of individually-enableable unit buffers. The reconfiguration logic module can enable only such unit buffers whose current handling contributions are necessary to drive the approximated or measured load to be driven.

Autonomous selection of output buffer characteristics as determined by

A programmable output buffer has source/sink characteristics that may be programmed to match the capacitive load to be driven. The programmable output buffer comprises a plurality of individually-enableable unit buffers, and a programmable unit buffer driver control logic. By programming the control logic to enable only such unit buffers whose current handling contributions are necessary to drive the output buffer load capacitance, current spiking can be minimized. The unit buffers preferably are scaled so each can source or sink a different magnitude current relative to the other unit buffers, a range of output buffer current may be programmed in discrete current steps. The control logic preferably includes elements that delay delivery of an enabling signal to various of the unit buffers. In a cascade-up mode, the control logic sequentially delays enabling signals so that various of the required unit buffers are enabled sequentially, to minimize problems associated with current spiking. In a cascade-down mode, the unit buffers are simultaneously enabled but are sequentially disabled. A mode encompassing cascade-up and cascade-down mode operation is provided, as is a mode wherein the sequence of cascade-on and/or cascade-off enabling signals is retriggered for every data change. This mode permits changing data in the buffer without creating current spikes that would result if the data were changed while the unit buffers were enabled.

Growing community of inventors

San Jose, CA, United States of America

John Chester Masiewicz