Advanced Micro Devices Corporation

John Chen

Sameer S Haddad

Colin Stewart Bill

Ravi S Sunkavalli

Ravi Prakash Gutala

Wing Han Leung

Jonathan S Su

Vei-Han Chan

Vei-Han Chen

A memory device having multiple banks, each bank having multiple memory cells and a method of programming multiple memory cells in the device wherein a bias voltage is applied to a common source terminal of the multiple memory cells and a time varying voltage is applied to gates of the memory cells that are to be programmed. In one embodiment, the voltage applied to the gates of the memory cells to be programmed is a ramp voltage. In a second embodiment, the voltage applied to the gates of the memory cells to be programmed is an increasing step voltage. In another embodiment, the bias voltage applied to the common source terminal and the voltage applied to the control gates of the memory cells to be programmed are selected so that the current flowing through cells being programmed is reduced and that the leakage current from memory cells that are not to be programmed is substantially eliminated. In another embodiment, a bias voltage is applied to the common source terminal and a bias voltage is applied to the common well voltage. The combination of the voltages applied to the control gates and to the sources decreases loading on the bitlines to ensure that V,does not fall below a required level necessary for the maintenance of the hot carrier effect during programming. A bias voltage can also be applied to the wells of the memory cells while the common source terminal is held at ground. Feedback control of the programming gate voltages can be used to control the power required for programming.

Multiple byte channel hot electron programming using ramped gate and source bias voltage

A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of floating gate transistor memory cells, a plurality of wordlines connected to the cells and a power supply for generating erase pulses. A controller controls the power supply to apply an erase pulse to all wordlines which are not deselected. Then, an erase verify procedure is applied to the cells in sequence. If all cells connected to a wordline pass the erase verify test, the wordline is deselected such that subsequent erase pulses will not be applied to the wordline and possibly cause the cells to become overerased. In one embodiment of the invention, erase verify is performed on all of the cells after an erase pulse is applied. The erase operation is completed when all cells pass erase verify. In another embodiment, erase verify is applied to each cell in sequence, with erase pulses being applied until each current cell passes erase verify. The wordlines can be deselected individually or in groups. The invention results in a tightening of the threshold voltage distribution of the cells.

Method for erasing flash electrically erasable programmable read-only

A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, and a power source for supplying a plurality of voltages to the cells. A controller controls the power source to apply at least one erase pulse to the cells. Then, at least one overerase correction or 'soft programming' pulse is applied to the cells during which the source, drain and control gate voltages of the cells are such that the threshold voltages of overerased cells will be increased, but least erased cells will not be disturbed. The overerase correction pulses thereby tighten the threshold voltage distribution. A source to substrate bias voltage is applied for the duration of the overerase correction pulses which reduces the background leakage of the cells to a level at which the overerase correction operation can be effectively performed, even in applications with low supply voltages.

A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) includes a semiconductor substrate, and a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate formed on the substrate. A controller controls a power source to apply an operational pulse to the drain of a cell, and apply a source to substrate bias voltage to the cell while the operational pulse is being applied thereto, the bias voltage having a value selected to reduce or substantially eliminate leakage current in the cell. The operational pulse can be an overerase correction pulse. In this case, a voltage which is substantially equal to the bias voltage is applied to the control gate for the duration of the overerase correction pulse. The operational pulse can also be a programming pulse. In this case, a voltage which is higher than the bias voltage is applied to the control gate of the selected wordline for the duration of the programming pulse. The bias voltage is preferably applied during both the overerase correction and programming pulses, reducing the power requirements and reducing the background leakage of the cells to a level at which program, read and overerase correction operations can be operatively performed.

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Cupertino, CA, United States of America

John Chen